Careful EUV Lithography Adoption for Intel 4
One of the biggest changes in Intel 4 is the introduction of EUV lithography tools for select layers. Samsung, TSMC, and Intel all target different applications and are pursuing different approaches to EUV. Generally, Intel tends to be fairly conservative about lithography. EUV was always considered for the 10nm family, but it was not ready for volume manufacturing in the right time frame, approximately 2017, particularly for high-performance logic applications. Instead, the company used self-aligned quad-patterning (SAQP) for metal layers and vias requiring 40nm pitch and below.
One factor in play is that while Intel has its own EUV mask-making subsidiary, the company is relying on the industry (i.e., ASML and now Mitsui) for pellicles that protect the masks from persistent defects caused by particles . The pellicle does not perfectly transmit EUV illumination and will reduce the intensity delivered to the wafer by twice the transmissivity, reducing tool throughput and increasing cost. For layers with dense patterns such as the metal interconnects, a pellicle is mandatory – the risk of a particle hitting an active portion of the pattern is simply too high. However, some sparser layers e.g., contacts and vias may be feasible to print without a pellicle. The ASML pellicle has been under development for quite some time, but only reached 90% transmissivity in early 2021 and will continue to improve over time.
In contrast, TSMC developed its own pellicle in 2019, which enabled ramping EUV into volume with Apple’s A14 on the 5nm node. In prior presentations, TSMC demonstrated that a single EUV exposure could potentially replace 4-5 different exposures using 193 immersion lithography thereby simplifying the overall process and actually achieving a roughly 10% reduction in the number of masks.
As Figure 8 illustrates, Intel is employing EUV where it replaces multiple immersion lithography exposures and substantially simplifies the overall process flow. In this particular example, 5 immersion lithography exposures (and subsequent processing steps) are replaced by a single EUV exposure and the associated steps. Reducing the number of exposures and process steps has significant secondary benefits such as improving variability and wafer cycle time. In particular, decreasing the number of exposures will reduce edge placement errors caused by overlay uncertainty and generally reduce processing time (which is typically estimated at ~1.5 day per mask).
While Intel did not disclose the exact layers where they are using EUV (or how), the overall benefit is shown in Figure 9. Without EUV the mask count would have increased by approximately 30% over the Intel 7 baseline. In reality, the total number of masks for the Intel 4 process decreased by 20%, a significant simplification that will increase yield and reduce cycle times. The overall number of process steps (e.g., including deposition, etch, clean, polish) decreased by a more modest 5%.
That being said, Intel’s adoption of EUV appears to be more selective and judicious than TSMC or Samsung and with different aims. EUV is an incredibly expensive technology and all things being equal, reducing the usage will improve the economics of manufacturing, reducing capital expenditure and wafer cost. Both of the foundries use EUV for contacts, vias, and metal layers below 40nm pitch to enable the tightest metal pitches. In contrast, Intel appears to be adopting EUV for contacts, but only a portion of the metal layers and vias.
As previously discussed, the contacts for Intel 4 almost certainly rely on EUV. However, in an ironic twist the only sub-40nm pitch metal layer, the 30nm M0, is still formed using SAQP . This is quite an interesting choice as it implies that the overall economics of SAQP are superior to single-exposure EUV in some situations. While this runs counter to the prevailing narrative, it is likely a reflection of the different strengths of EUV and SAQP patterning and may also be tied to the current throughput impact of the pellicle.
Moving up the interconnect stack, the M1-M4 layers are all loose enough pitch that self-aligned double patterning (SADP) with restricted layout is a viable option – similar to the approach employed for Intel’s 10nm and 14nm process technologies. That being said, it appears that Intel is using EUV in some of these metal layers. Printing a metal layer with EUV would allow forming more complex shapes and more flexible design rules, which would simplify layout for automated design tools and help increase density. It is even possible that EUV would enable fully bi-directional routing, essentially collapsing two orthogonal metal layers and a via layer between them into a single metal layer and eliminating most edge placement error.
Hopefully future disclosures or teardowns will reveal exactly how many layers are using EUV and in what capacity.