Intel’s 45nm Surprise: High-k Dielectrics and Metal Gates

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Putting the Metal Back in (Complementary) Metal Oxide Semiconductors

Electrical fields are the basis of modern transistors. They control whether current can flow from the source to the drain, hence whether they are “ON” or “OFF”. The permitivity of a material, describes how well an electrical field can flow through a dielectric, and is quantified by a k-value. Low-k materials block electrical fields, while high-k materials permit fields to pass through. Generally, within the world of semiconductors, silicon dioxide (k=3.9) is used as a reference, and low or high-k just indicates a k value less than or greater than 3.9. Not too long ago, one of the major advances was the use of low-k (in the range of ~2.7) materials between different interconnect layers in a semiconductor process; this reduces parasitic capacitance and improves wire performance. However, this is very different from the subject at hand, which is the transistor gate, so don’t get confused.

Figure 2 – Transistor Materials

Figure 2 above shows two transistors, the first one is a conventional transistor, which uses SiO2 (K=3.9) as the gate oxide. On Intel’s 65nm process, the gate oxide is only 1.2nm thick, the charges tunnel through the gate, causing leakage. Additionally, during normal operation, a small region between the oxide and the electrode becomes depleted, degrading performance further.

The key difference is the high-k gate oxide, which uses a hafnium based material. The hafnium gate oxide is deposited using atomic layer deposition, to ensure that the gate is uniformly thick. There are a variety of high-k materials which have been examined, including hafnium oxide (HfO2), hafnium silicates (HfSiO or HfSiON) and quite a few others [1]. HfO2 for example has a k value of roughly 25, 6X better than SiO2. Since the hafnium based material increases the field effect, which controls the source-drain channel, the gate oxide can also be made thicker. The combined result increases Ion and lowers gate leakage. Figure 3 below shows the gate stack for the new transistors. While Intel would not disclose how thick the gate dielectric is, an eye ball estimate is ~2-2.5nm, and many of Intel’s initial papers described dielectric layers in that range.

Figure 3 – High-k Dielectric and Metal Gate Transistor Stack

Since polysilicon is not compatible with Intel’s high-k material, the newer 45nm transistors use a metal gate. Mark Bohr indicated that two different metal materials are used, one for PMOS transistors and one for NMOS transistors; although he declined to elaborate on which particular materials were used for competitive reasons. In the latter part of the year, when processors using 45nm are available, the materials will likely be disclosed at IEDM or another suitable conference. Initial research from Intel at IEDM focused on using Nickel-silicide for both PMOS and NMOS, but apparently better solutions exist. Because no depleted regions will form with the metal gate, the transistor has better control over the channel between the source and the drain. This finer control will improve Ion, and lower subthreshold leakage.

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