Eleven years ago Intel startled the world by introducing the first one million transistor microprocessor at the International Solid State Circuits Conference (ISSCC) in San Francisco. That processor’s full name was the 80860, a 32-bit RISC processor. Generally known just as the “i860”, it was developed as a numeric coprocessor for use in x86-based computers under the code name “N10”. But ever opportunistic, Intel decided to market it against competing RISC processors for the technical workstation and server market.
The Intel i860 was, in most respects, a conventional RISC processor. It had thirty two 32-bit general purpose integer registers R0 through R31 (R0 always read as zero), and thirty two 32-bit floating point registers F0 through F31 that could be used in even/odd pairs to store 64-bit floating point values (F0 and F1 always read as zero). The i860 instruction set had a sparse but functional (albeit awkward at times) collection of the normal integer, logical, branch, and memory operations. It occupied a 155 mm2 die manufactured in a 1.0 um two level metal CMOS process. The i860 included 4 Kbytes of instruction cache and 8 Kbytes of data cache, each two way set associative, and a 64-bit wide data bus.
But the i860 had three unusual features. The first was a small set of instructions to support 3D image rendering. The graphics unit was a small appendage to the i860’s muscular floating point hardware and it implemented instructions for pixel intensity interpolation, z depth interpolation, and z buffer checking. The second was the i860’s ability to enter and exit dual instruction issue mode under the control of a bit in the instruction word. In dual instruction mode the i860 could issue one core (integer) and one floating-point instruction every clock cycle. Unfortunately there was a two-cycle latency in entering and exiting dual instruction mode so it was hard to use except in carefully handwritten assembly language computational and graphics kernels. This scheme is shown in Figure 1.
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