“Those who do not remember the past are condemned to repeat it.” -George Santayana
“Hegel remarks somewhere that all great world-historic facts and personages appear, so to speak, twice. He forgot to add: the first time as tragedy, the second time as farce.” – Karl Marx
The important thing to remember is that IA-64 compilers have to explicitly schedule instructions and defined dependency relationships between groups of instructions and employ complex mechanisms like register rotation to achieve good performance and make up for the rigidity imposed by IA-64’s in-order execution scheduling model. So in a real way the compiler is even more important for the competitiveness of IA-64 processors than it was for the i860. If i860 compilers didn’t employ the tricky features of that architecture the i860’s performance level was still comparable to competing RISC processors like MIPS and PA-RISC. But if IA-64 compilers cannot extract enough benefit from things like explicit instruction grouping of independent instructions, predication, and register rotation, then IA-64 processors will not be as competitive as superscalar RISC processors with comparable implementation complexity and technology that enjoy the benefits of dynamic instruction scheduling and large physical register files supporting true register renaming.
Has Intel learned anything from its ill-fated venture into the technical computing market with the i860? All indications are that they at least recognize their mistakes committed a decade earlier and are trying to avoid repeating them ten years later. How successful they are is another matter. For one thing, the HP conceived IA-64 architecture is the product of compiler research both at the HP research labs using architectural test benches such as Playdoh, and work at universities such as the Impact compiler effort at the University of Illinois at Urbana-Champaign under Dr. Wen-mei Hwu. This contrasts sharply with the i860 where the architectural innovation derived from chip designers exploiting new freedom in VLSI processor implementation using one million transistors. So in a sense i860 novel features were solutions in search of a problem and it was left up to compiler writers to scratch their heads and figure out which if any of the new features could be exploited using the compiler technology of the day.
Another factor enjoyed by IA-64 but wasn’t by the i860 is the support infrastructure and lead time afforded to the development of application and operating systems by independent software vendors (ISVs). Preliminary compilers and architectural simulators have been in the hands of software developers under non-disclosure agreements for several years now. In fact when the first silicon prototypes of the Merced (Itanium) processor appeared last September there already were several operating systems available to boot on it. Intel has gone so far as to bankroll a $250 million venture capital fund to support the development of native IA-64 software applications. This is completely in contrast to Intel’s attitude when it introduced the i860 of “build it and they will come”. As extra insurance against a shortage of native applications, IA-64 processors include a special operating mode for execution of x86 CISC programs, albeit at a much lower performance level than native IA-64 programs or contemporary x86 processors. Intel also conducted a similar parallel effort towards of greasing the skids for IA-64 adoption by major computer manufacturers. For years Intel spread fearsome tales of how incredibly powerful their new IA-64 processor family would be and how competing RISC designs couldn’t possibly keep up. This campaign of preemptive psychological warfare was largely successful in slowing development programs within many RISC processor lines. The biggest victory occurred when the credulous, terrified management at SGI announced they had canceled development of two high-end MIPS processor designs known as “the Beast” and “H2” and SGI would adopt IA-64 in their place.
However, SGI’s policy of accommodation with Intel backfired when the first IA-64 processor Merced suffered an embarrassing series of delays and SGI’s aging MIPS line was left increasingly vulnerable to competitors, such as HP (which continued to aggressively develop its PA-RISC processor line despite being the originator and brains behind the IA-64 architecture and publicly committed to eventually replacing PA-RISC with IA-64). In contrast, the i860 appeared suddenly on the scene as a surprise after most computer system vendors had already chosen sides in the ongoing competition between competing RISC designs and these companies were reluctant to switch CPU horses in mid-stream. And also the i860 couldn’t really run technical applications any faster than most of its competitors.
In many ways Intel’s upcoming launch of its IA-64 line of 64 bit RISC-like processors into the technical workstation and technical and commercial server markets is eerily reminiscent of the disastrous launch of the i860 eleven years ago. The same Intel hype and full court press by their powerful marketing department seen today was in evidence and the trade press then and now unfortunately mostly mirrored Intel’s party line word for word. Most observers thought that the new processor would rapidly take share away from competing RISC processor families as easily as the x86 defeated the Motorola 680×0 line in the earlier battle for supremacy in the CISC processor market.
But an astonishing thing happened. The technical computing market basically ignored the i860 and it quickly vanished off the radar screen. Intel has apparently corrected many of its original mistakes for the launch of the IA-64 family. However, the IA-64 design is inherently far more vulnerable to deficiencies in its compilers than the i860 ever was. So its technological success is far from assured. However, considering the size of the investment and public corporate commitment Intel has placed in IA-64, and the reassurance of x86 compatibility, it is unlikely to be a commercial failure.
Discuss (16 comments)