Notes from ISSCC 2001

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Alpha EV7: Powerful but Late, New EV68 to Hold the Fort

Two of the three Alpha papers Compaq presented described the EV7. This highly integrated server oriented processor has 152m transistors on a 21.1 x 18.8 mm (397 mm2) die and will be manufactured in a 0.18 um bulk CMOS process using 7 levels of copper interconnect. It is described as consuming 125 W at 1.5V when clocked at 1.2 GHz. It incorporates a slightly modified EV6 processor core along with 1.75 MB of L2 cache, dual memory controllers, and quad inter-processor communication ports with associated packet router. The floorplan of the EV7, which will be packaged in a 1443 pin LGA, is shown in Figure 1.

Figure 1 Floorplan of the Compaq Alpha EV7

The L2 cache is a seven way set associative, write back design with ECC protection and delivers 19.2 GB/s of peak bandwidth at 1.2 GHz. Each of the two memory controllers supports four direct Rambus channels for a total peak memory bandwidth of 12.8 GB/s. Each controller has a 28 entry memory request queue and can support up to 1024 open pages. The router drives four interprocessor communication links that connect to other EV7 devices in a multiprocessor system. Each link provides up to 6.4 GB/s of bandwidth for communicating remote memory request and cache coherency packets. The router is implemented as an 8 x 7 crossbar with distributed arbitration and supports buffering of up to 200 packets. The EV7 has a pin to pin packet routing delay of 13 clock cycles. The link transmits two data beats for every three CPU clock cycles, which corresponds to 800 Mbps per pin. Each link is likely composed of two 32-bit wide unidirectional data paths operated in a double data rate (DDR) fashion at 400 MHz.

While the EV7 is more impressive with each new disclosure of information, one important fact cannot be overlooked. During the ISSCC presentation it was said the EV7 would be ‘released to manufacturing shortly’ which can only interpreted as it hasn’t taped out yet. Aside from apparently violating the unwritten ISSCC prohibition on submissions describing ‘paper chips’ (McKinley?), it means we aren’t likely to see EV7s based systems commercially shipping until about 2Q02 at the earliest. The third Alpha paper from Compaq described the MPU that will likely be their 64-bit mainstay until EV7 finally appears, the second generation EV68.

As I have mentioned in an earlier article (See Looming Battle in 64-Bit Land), the EV6 is entering the world of 0.18 um process technology rather lethargically. The original EV68, described a year ago at ISSCC 2000, was effectively a hybrid device that used 0.18 um transistors, but kept the metalization design rules and approximate die size of the 0.25 um EV67. Manufactured in a 0.18 um aluminum process, the first EV68 was a hefty 193 mm2 in area and was limited to 1.0 to 1.1 GHz clock rates. This processor has just started full-scale shipping in Compaq systems at 833 MHz, a clock rate overlapping the fastest speed grade of the 0.25 um EV67.

The second generation EV68 is a true 0.18 um device manufactured in the same bulk CMOS copper process as the EV7. It features a more economical die size of 120 mm2. It can operate up to 1.4 GHz under nominal conditions, despite the fact that its designers restricted the usage of low VT transistors to about 2% of the 15m transistors in this chip. Compaq estimates the performance of the EV68 at 800 SPECint2k and 1000 SPECfp2k while consuming a relatively modest 65 W. The new Alpha will likely initially ship at 1.0 or 1.1 GHz. Hopefully, Compaq can reduce the silicon and system qualification times for the second generation EV68 from the more than one year it took for the 0.25/0.18 um hybrid device. If so, we may see shipping Alpha systems break the 1 GHz level before 2002. Also reportedly in the works is a second-generation Tsunami chipset that supports faster system bus and memory clock rates to help keep pace with the faster EV68.

The new device is significant in that it shows that the EV6 core can scale nicely in clock frequency with process shrinks. With a bit of work, it may exceed 1.6 GHz in a 0.18 um SOI copper process. More problematic is the design of an external L2 cache that can keep itself from becoming a performance bottleneck at 1 GHz and above. Perhaps the curious omission of even a modest on-chip L2 cache is part of Compaq’s product positioning strategy to permit the sale of moderate cost EV68 for desktop systems and premium priced EV7 for high end servers. If Samsung chooses to be aggressive in pricing its 21264E MPU (EV68 with 1.75 MB of L2 cache), it may upset this hypothetical two tier Alpha strategy.

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