PA-RISC: Riding the Process Shrink Highway in Cruise Control
Five years ago HP released the PA-8000, its first venture into both 64 bit computing and out-of-order execution processor design. That was about the same time that Intel shipped its first incarnation of its long-lived P6 core in the form of the Pentium Pro. The 0.5 um PA-8000 later underwent a makeover and major tune-up in the same process and was re-christened the PA-8200. The PA-8000 and PA-8200 were best known for their massive off-chip single level caches and achieving high performance at modest clock rates. The PA-8000 core was ported/shrunk into Intel’s 0.25 um process where it was mated to 1.5 MB of on-chip L1 cache. This device, known as PA-8500, was huge (about 477 mm2) yet still managed to turn in respectable clock frequencies and performance. Repeating the pattern of the PA-8200, Intel reworked the PA-8500 and renamed it the PA-8600, which is currently HP’s top of line RISC processor.
While Intel has since created an all-new x86 processor core to replace P6, HP is strictly in platform maintenance mode with PA-RISC. Having publicly committed itself to a transition to IA-64, their strategy is to ride their five year old PA-8000 core as far into the future as possible. HP is gambling that by the use of further process shrinks and cache enhancements they can create a series of 64-bit MPU products based on the PA-8000 core that are competitive enough to retain the bulk of their PA-RISC customer base until they can finally be transitioned onto IA-64 based platforms.
HP’s latest effort at VLSI recycling is the PA-8700. It is a shrink of the PA-8600 into a 0.18 um SOI CMOS process with seven levels of copper interconnect. Rather than waste the entire benefit of the process shrink simply reducing the die size, HP decided to partially offset it by increasing the size of the on-chip caches by 50%. The PA-8700 incorporates a 1.5 MB data cache and 0.75 MB instruction cache. In addition, the number of TLB entries was doubled to 240. Fast process silicon is yielding parts that operate up to 1.0 GHz at 70 deg C and 1.5V.
Power dissipation is a remarkably low 45 W at the ‘target frequency’, a testament to some good circuit design and the benefit of SOI processes in reducing parasitic capacitance of transistor source and drain regions. To ensure correct operation, many circuits had to be modified to account for the history effect of floating body voltages and increased susceptibility of dynamic signal nodes to corruption from coupled signal noise and charge sharing. PA-8700 silicon has already booted Unix in single and multiple processor configurations, so we could conceivably see it ship in commercial systems later this year. The initial devices will likely be clocked at about 800 MHz.
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