POWER4: CMP could stand for Chip designed in Many Places
Unlike most of the other high end MPU papers at ISSCC, IBM’s POWER4 presentation focused on the design and engineering management techniques used to keep this highly complex project on track. This was a particular problem for IBM because the POWER4 design team was scattered across six different sites, and individual engineers on these teams differed significantly in experience and know-how due to the almost universal problem of staff turnover. As a result, IBM was forced to impose a regimented, almost military-like “by the numbers” design methodology on its scattered forces. The design was divided up hierarchically, and individual teams signed up to ‘contracts’ to meet a target specification and schedule for their assigned blocks. Rigorous inter-team peer reviews were held before any block could be signed off.
Certainly the POWER4 project required organizational discipline. The POWER4 implements two complete four-way, superscalar, out-of-order 64-bit PowerPC CPUs in a 0.18 um SOI CMOS process with seven layers of copper interconnect. The 174m transistor device integrates three independent 512 KB L2 caches, controllers for external L3 cache and memory, and inter-processor communication links. The POWER4 is composed of over 4000 instances of 1015 unique macros including 442 custom logic blocks, 523 synthesized macro blocks, and 50 different SRAM designs. POWER4 managers expected first silicon to have roughly a dozen minor bugs requiring mask revision. However, the imposed discipline has reportedly worked well and first silicon has experienced less than half the expected problems.
Existing POWER4 silicon is running over 1.1 GHz. Testing indicates that the actual power consumption might be a bit less than the simulated worst case power of 115 W at 1.5 V, with each CPU consuming 30 W. Like the EV7, the POWER4 does not employ clock gating. As a result, the POWER4 burns around 70% of its power in clock generation, distribution, and use in latches. The huge disparity in power consumption between POWER4 and the PA-8700, which is likely implemented in the same SOI process, is not surprising when you consider that the POWER4 includes two processors and nearly half its power is consumed outside those two processors. The first POWER4 based products could potentially ship before the end of the year.
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