Notes from ISSCC 2001

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Miscellaneous

ISSCC features a comprehensive display of electrical engineering and solid state physics text books from a variety of leading publishers. One book I purchased was ‘Design of High-Performance Microprocessor Circuits’ edited by Anantha Chandrakasan, William J. Bowhill, and Frank Fox and published by IEEE Press (ISBN 0-7803-6001-X). It is comprehensive (PLL and DLL design, I/O & ESD circuits, embedded DRAM are all covered) and up to date (It includes references as recent as 1999 and specific examples of design techniques from MPUs as recent as the Alpha EV6 and PowerPC G3). If Hennessy and Patterson’s architecture text is the ‘bible’ for the computer science side of MPU design, then ‘Design of High-Performance Microprocessor Circuits’ can be considered its equivalent for the electrical engineering aspect. I do have to caution that it is expensive (over US$ 100 for non-IEEE members) and likely incomprehensible to anyone without at least a basic understanding of electronics and digital logic.

Commentary and Conclusion

The 2001 ISSCC conference shows that chips designers are far from running out of new and promising ideas to increase the performance and capabilities of microprocessors, memory devices, and other types of integrated circuits that power the gadgets we rely on in our professional and personal lives. The non-x86, non-embedded control MPU market is alive and well and slowly bringing to market staggeringly powerful processors that will define ‘big iron’ for the next 3 or 4 years. The withdrawal of the McKinley IA-64 MPU paper brings to mind a comment once made about gallium arsenide (GaAs): It’s the technology of the future. And it always will be. In the publicly disclosed realm, the IBM POWER4 and Compaq Alpha EV7 look like the top contenders for MPU server heavy weight performance champ of the world on the strength of their powerful CPU core(s), large integrated L2 cache(s), and high memory and interprocessor communications bandwidth capabilities.

With its recent transformation of its 37 year old 32-bit mainframe architecture to 64 bits, and a possible road map for incorporation of superscalar, out-of-order execution capabilities, it appears that IBM wants to have two credible high-end proprietary architectures in its stable in addition to its public commitment to IA-64. Having three 64-bit platforms should make life interesting, and problematic, for IBM’s server marketing strategists. After all, Sun Microsystems has shown that concentrating all efforts on a single MPU family, even a perennially weak one like SPARC, can be very successful if marketed adroitly.

The Pentium 4 continues to be a bit of a mystery. Many details about its clocking and double speed execution units were revealed at ISSCC. This MPU relies on a good deal of innovation in both areas to achieve up to 2 GHz processor and 4 GHz ALU clock rates in a 0.18 um aluminum process. The mystery is how Intel could bring to market a design which loses much of the its performance potential running a significant part of the current PC software installed base. Can Intel induce software vendors to recompile performance critical applications with Pentium 4 aware compilers? Or will it be forced to include corrective design changes in future versions? There is historical precedence for the latter. The Pentium 4’s architectural predecessor, the P6 core, was modified to enhance performance of 16-bit legacy code in the move from the high-end Pentium Pro to the mass market Klamath Pentium II.

Finally, even the mighty POWER4 and EV7 have to bow to the lowly game console when it comes to memory bandwidth that can be provided by the creative use of embedded DRAM, albeit for a relatively tiny amount of memory. Despite the obvious advantage for specific applications (what could you do with a palm computer with 32 MB of 10 or even 100 Gbyte/s integrated memory?), the future of embedded DRAM is clouded by the divergence of process technology between high speed pure CMOS logic processes and slower DRAM technologies with less leaky transistors and junctions. I hope the use of this promising technology won’t be restricted to large, vertically integrated companies with the vision and deep pockets to fund costly, narrow focused IC and process development programs that can take years to reach market.


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