ISSCC 2005 Coverage: Day 1

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What is ISSCC

The IEEE International Solid-State Circuits Conference brings together three thousand engineers from all across the world to the Mariott Hotel in downtown San Francisco each year. In what’s affectionately known as the “Chip Olympics,” the latest and greatest technologies to be implemented in silicon are presented and discussed, partially to disseminate new information among the knowledge workers of this world, and partially to boast of new accomplishments.

ISSCC acts as a gateway between industry and academia. Notably, of the ten institutions which are presenting the greatest number of papers, exactly half are technology-oriented businesses, and half are Universities. Achievements and new discoveries in these twin towers are allowed to osmote back and forth so that industry stays modern, and academia stays relevant.

The theme of this year’s conference is, “Entering the Nanoelectronic Integrated-Circuit Era.” With nearly 3500 attendees, 200 technical papers will be presented in 31 different sessions, and the vast majority of them are targeting the new problems encountered by shrinking transistor dimensions to below the 100nm scale. These problems include sub-1.2V power supplies, sub-threshold leakage currents in both analog and digital circuits, and quantum effects which are showing significance for the first time as transistors continue to follow the incredible shrinking path towards the infinitesimal.

Advanced Memory Design Forum

THe main ISSCC conference is preceded and followed by 8 tutorial sessions and 5 advanced forums. Since the tutorials and forums run in parallel, it was decided that the advanced forum on memory design would be the most interesting and illuminating relative to the papers that will be covered in the next 3 days.

Forum 1 – High Speed DRAM Design Issues

Young-Hyun Jun – Samsung Electronics

This presentation covered several important issues in modern DRAM design, such as the trade-offs between delay-locked loops (DLLs) and phase-locked loops (PLLs) for clock frequency synthesis (clock multiplication). Beyond the technical details, the speaker discussed the cost-effectiveness of DLLs for low-frequency applications, and that it has the added advantage of having a simple and straightforward topology. However, it was conceded that, for frequencies in excess of 500MHz, PLLs tend to be the superior option.

Interestingly, the presentation also covered Vernier delay lines. A Vernier delay line is a programmable circuit which is used to vary the delay of a signal to its destination. An example of a VDL can be seen in Figure 1 below.

Figure 1 – Vernier Delay Line

By programming the switches, it is possible to vary the skew from 4*t_f (a small delay) to 4*t_s (a much larger delay). One practical application of such circuits is as a programmable de-skew circuit for clock signals. Notably, Intel will be discussion their use of clock Vernier devices for their region-based clock de-skew system in Montecito in a paper presentation this Tuesday (February 8, 2005).

Forum 2 – High Speed DRAM I/O

Terry Lee – Micron Technology, Inc.

Many questions as to why the DRAM market doesn’t appear to keep up with the microprocessor market can be answered with an economic explanation rather than a technical one. This presentation began by stating the economic realities of the DRAM market, and the constraints that these realities impose on DRAM design and implementation. The role that DRAM plays was stated succinctly at the beginning of the talk: “DRAM’s role in the semiconductor chain is to be lowest cost-per-bit with reasonable data rates and access times.”

The speaker also presented an overview of past, present, and future commodity DRAM technologies. It was stated that GDDR3 exceeds the performance of DDR2 for several reasons. Some of these reasons include the fact that the former only operates in a point-to-point or point-to-two-points topology, and that it has superior, on-die I/O power decoupling. The speaker indicated that in order to scale DDR memory to higher clock rates, it would have to adopt a topology resembling that of GDDR3. The DRAM companies have recognized this, and the DDR3 specification is similar to that of GDDR3: strictly 1 module per data channel, and command/address signals daisy-chained across modules.

Lastly, the value of package and power modeling was emphasized. Current modeling techniques typically involve taking a cross-section of the package and power network and performing a 2D analysis. The problem with this approach is finding a 2D cross-section which is representative of the entire device, and that is a difficult task, if not an impossible one. The speaker ended on a passionate note, stating that “[he] can’t emphasize how important power modeling is.”

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