Every year the International Solid-State Circuits Conference (ISSCC) is held at the San Francisco Marriott, so that chip design companies can show off the tricks and techniques used in their latest technological marvels. ISSCC is sponsored by IEEE Solid-State Circuits Society, the local Santa Clara chapter and the University of Pennsylvania – however, the event is largely co-ordinated by graduate students and staff from the University of Toronto. However, the scope of the event is clearly international – for most European and Japanese companies, the long and expensive flights dictate that only a few events each year can be attended, and ISSCC is the conference of choice.
Well over 4000 attendees showed up, for tracks ranging from PLL design, to the ever popular analog and MPU sessions. This year’s ISSCC was quite interesting and featured a wide variety of presentations, often scheduled at mutually exclusive times. There were two papers in the emerging technology track on the use of carbon nanotubes, both from IBM Research. The circuit design forum, which occurs the day before ISSCC had a very interesting session on 3D integration, with presentations from IBM, Intel, Georgia Tech, DARPA and others. While the sessions are usually quite valuable, one of the best parts about ISSCC is that it brings together an incredible range of talented engineers in a single venue, and the ensuing discussions are always very enlightening.
Our coverage of ISSCC will be split into several parts. This first part will cover several sessions from the MPU track in moderate detail, particularly those concerning PA Semi, Intel’s Merom, Sun’s Niagara II and NEC’s early defect prediction. Later articles will go in-depth on a single subject, such as Barcelona and Intel’s Polaris.