ISSCC 2012 Preview

Just before Thanksgiving, the advanced program for ISSCC was released. While the conference takes place in February 2012, the program includes a brief listing of the tutorials and papers, which builds anticipation for the event. Of course, the presentation titles also give insight into the actual proceedings and are worth discussing in the absence of the papers.

Some of the highlights for ISSCC will be the first papers discussing 22nm. Ordinarily, IEDM is the venue of choice for disclosures of novel process technology. However, Intel has withheld any technical discussion of their 22nm FinFET process. Instead, the 2012 ISSCC will be the kickoff for 22nm disclosures. As a result, there is a unusually large number of papers from Intel describing components and SoCs on their FinFET process. Other highlights include several microprocessor and SoC papers from AMD, Cavium Networks and Oracle. Looking out further to the future, the clear focus is power consumption. There are several papers from Intel on low-power logic, one from IBM discussing 3D integration of embedded DRAM and a third from Fujitsu that focuses on system level power for the K supercomputer.


The perennially popular processors session (#3) has returned, although there is only a single track this year. Last year, there were so many papers that the organizers had two sessions, one for enterprise designs and one for mobile and low power. The processor track includes no less than three product papers from Intel. The first describes the 22nm Ivy Bridge SoC and will hopefully delve into the details of the CPU and GPU design on Intel’s novel FinFET process. The second product paper concerns a 32nm dual-core Atom SoC with a WiFi transceiver, which presumably refers to Clovertrail (the tablet oriented version of Medfield). The last paper focuses on an all-digital clock generator in the low-power variant of Intel’s 22nm manufacturing, which presumably will be used for future mobile devices.

AMD will discuss clock distribution for a power-efficient microprocessor, which could refer to SoCs based on the low-power Bobcat core or the new Bulldozer. Outside x86, there are two papers on classic RISC architectures. The first is from Cavium Networks and describes a 32-core MIPS-compatible design, which is the successor to the existing Octeon family. Last, there is a paper from Oracle that focuses on the S3 core, which is the basis of the recently released T4 family of throughput microprocessors. This is the first successful out-of-order design from Oracle and should be a very interesting comparison to similar efforts from AMD, IBM and Intel. The S3 is much more likely to rely on a highly automated design approach, in contrast to more heavily optimized x86, Itanium and PowerPC microprocessors.

Low Power Logic

At last IDF, Intel Fellow Shekhar Borkar spoke about the potential for Near Threshold Logic (NTL) to fundamentally improve energy efficiency and continue Moore’s Law scaling. The essence of NTL is operating on a very low supply voltage that is only marginally higher than the threshold voltage (where transistors conceptually start to turn ‘on’).

The Microprocessor Technology Lab has been developing circuit techniques for Near Threshold Logic, and at ISSCC they will present a collection of papers on the subject. The first paper is in the processor track and describes a 32-bit x86 microprocessor that is implemented in 32nm and can operate from 280mV to 1.2V; and there should be a demonstration unit at the conference. The three other papers are in the session 10, on high-performance digital logic. They include a single precision FP fused multiply-accumulate unit and a lighting accelerator for 3D graphics, both of which are fabricated on 32nm and operate at 300mV and 560mV respectively. The last paper will describe a 22nm reconfigurable 256-bit wide SIMD permute unit that scales from 280mV up to 1.1V, exhibiting a 9× improvement in energy efficiency.

In the context of Near Threshold Logic, the most interesting aspect will be the cost of low-voltage operation and the energy efficiency gains. Generally, frequency drops linearly with voltage, while power decreases quadratically, but it is possible that the curves work out differently as the supply voltage approaches the sub-threshold voltage. There is also likely to be a cost in terms of die area and design complexity, which bear watching. Overall, this logic family seems like a natural fit for throughput oriented designs, and the trade-offs should clarify whether this is also a good fit for mainstream SoCs and perhaps when we can expect to see the use of NTL in products.

SRAM, DRAM and Supercomputers

Coinciding with Intel’s discussion of Ivy Bridge, the company will also describe their 22nm SRAM building blocks. There are at least two flavors: density optimized (e.g. for an L3 cache) and low-voltage optimized (e.g. an L2 cache). The density optimized cells were fabricated in a 162Mbit array and are 0.092µm2. Overall, Intel reported a 54% shrink, higher performance, and lower minimum voltage; the latter due to assist circuitry.

IBM and Intel are the two leaders in terms of digital logic. While there are a huge number of papers from Intel, there are far fewer from IBM simply due to the latter’s manufacturing and product timelines. There are several IBM papers that focus on high-speed I/O for 45nm and 32nm SOI. However, the most intriguing paper from IBM describes a 3D integration test, that stacks 45nm eDRAM above a test chip. The eDRAM is connected with finely pitched TSVs, and interlayer memory accesses are reported at an amazing 2.7GHz. This is roughly half the core clock of IBM’s fastest microprocessors and is probably a hint of what to expect in the POWER8 and future generations of zArchitecture mainframes.

The last paper in the high-performance digital session is from Fujitsu and describes the K supercomputer at Riken. In addition to being the fastest supercomputer on the TOP500, K is also one of the most power efficient (#31 by GFLOP/s per watt) – beating out many systems relying on GPUs. Riken’s K is based on the SPARC64 VIIIfx with a custom 6D interconnect. An earlier article explored the relationship between cooling, performance and power, using the K supercomputer as an example. Hopefully, Fujitsu’s presentation will extensively discuss the system and processor level trade-offs that achieved such excellent power efficiency.

Overall, there are relatively few product papers focusing on new microprocessors. However, there are a tremendous number of papers that foreshadow product developments and discuss the underlying technologies that will be critical in the next several years. While unfortunately, the details of these presentations will have to wait till February, there is quite a bit to look forward to at ISSCC next years.

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