Conclusion
It is comforting to see the pace of innovation in the microprocessor field shows no sign of slackening. The great seesaw battle between Intel and AMD for share of silicon’s richest prize, the x86 microprocessor market, is about to enter a new phase with the imminent release of the 0.13 um Northwood Pentium 4. Although AMD will also migrate its K7 core to 0.13 um later in 2002 with both bulk and SOI versions, it is unlikely to be in the position to regain the performance advantage over Intel it previously achieved with the T-bird and XP Athlon until its new 64-bit Hammer core ships. Unlike AMD, Intel plans to reserve its 64-bit offerings for the high-end market. With McKinley Intel hopes to address the significant performance difficulties seen in the Itanium in part by taking advantage of its capacious manufacturing facilities to incorporate a huge amount of on-chip cache on its sizable die.
It seems like the time it takes for new ideas and features to migrate down from high-end server MPUs to mass-market devices is shrinking. The integration of high performance interprocessor communication links and memory controller(s) onto a processor die has been on the drawing board for many years and will soon be realized in the high end server market in the form of the EV7. Remarkably, the same concepts will appear in a mass-market x86 processor, the first of AMD’s Hammer series, not too much later. Although these features will naturally be more limited in the scope in the x86 device to keep costs under control, they should still provide a large boost in performance from significantly reduced memory access latency as well as a dramatic reduction in the cost of producing multiprocessor systems based on this device.
Few topics in the computer and microprocessor field can raise a controversy, as well as blood pressure, as quickly as benchmarks and benchmarking. Sun managed to throw a hand grenade into the simmering debate between the supporters and detractors of the industry standard SPEC CPU benchmark by speeding up the execution of one of the fourteen programs in the floating point suite by nearly an order of magnitude through the use of a previously unexploited compiler optimization. This in turn raised the SPECfp2k score of its latest US-III processor by roughly 20%. We can now look forward to the spectacle of competing firms scrambling to reverse engineer Sun’s new compiler trick and incorporate the same voodoo into their own wares.
References
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[2] Hennessy, J. and Patterson, D., “Computer Architecture A Quantitative Approach”, Morgan Kaufmann Publishers Inc., 1990, ISBN 1-55860-069-8, p. 181.
[3] Advance Program, 2001 IEEE International Solid-State Circuits Conference”, p. 35.
[4] Weber, F., “AMD’s Next Generation Microprocessor Architecture”, October 2001, Downloaded from AMD web site.
[5] Jain, A. et al, “A 1.2 Ghz Alpha Microprocessor with 44.8 GB/s Chip Pin Bandwidth”, Digest of Technical Papers, ISSCC 2001, Feb 6, 2001, p. 240.
[6] Dulong, C. et al, “The Making of a Compiler for the Intel Itanium Processor”, Intel Technology Journal, Q3 2001, Downloaded from Intel web site.
[7] Desikan, R. et al, “Measuring Experimental Error in Microprocessor Simulation”, Digest of Technical Papers, 28th Annual International Symposium on Computer Architecture, June 2001.
[8] “Intel OverSPECs Parts”, Microprocessor Report, January 22, 1996, Volume 10, Number 1, P. 5.
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