Waiting For McKinley
The importance of Intel’s McKinley processor to the success of its IA64 product line has been widely known since October, 1999. The disclosure of design details for the first IA64 processor Merced/Itanium was overshadowed by Intel architecture lab manager Fred Pollack’s unusual downplaying of Merced’s performance. After years of Khruschev-like “we will bury you” rhetoric directed at the makers of RISC processor and systems from the Intel and HP camp, the public dressing down of the first generation IA64 device, a processor that wouldn’t ship for nearly two years, was very surprising. And was yet another sign that the mammoth project to harness very long instruction word (VLIW) technology for general purpose computing wasn’t progressing well.
While delivering the bad news about Merced, Mr. Pollack also coined the phrase “Wait for McKinley” with the promise that its performance would “knock your socks off”. In fact, McKinley was described as offering at least twice the performance of Merced in the same process. McKinley can operate at higher clock frequencies than Merced/Itanium and has significantly more on-chip cache. But the practical limit to which both factors can improve the performance of an MPU design manufactured in the same semiconductor process strongly suggests that McKinley is also a much more efficient and better organized design. I will briefly review IA64 instruction encoding and its relevance to the relatively poor integer performance of the Itanium microarchitecture. This will lead directly to speculation about the nature of the McKinley design and the various approaches Intel and HP may have used to raise IA64 performance to a level befitting a processor immodestly named after the tallest mountain in North America.
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