As Intel’s first real system-on-chip (SoC), one of the other critical ingredients for Medfield is an on-die fabric for communication. Unlike Intel’s PC-oriented designs, there is considerable third party IP in Medfield, such as Imagination’s graphics and video codecs. The ARM ecosystem generally relies on the AMBA family of interconnects for integrating IP blocks into SoCs.
Intel’s equivalent is the Intel On-chip System Fabric or IOSF, which is a modular interface that simplifies design and re-use. IOSF is used for Intel’s own IP (such as the core and cache) and certain third party blocks in the system (perhaps the GPU). Most importantly, the ordering model for IOSF is the same as PCI, which is very helpful for compatibility with existing software and tools. Beyond PCI compatibility, few details are publicly available, but perhaps that may change over time. Medfield is one of the first implementations to use IOSF and many others will follow. It will be particularly interesting to see if future high-end designs like Haswell also use IOSF, which would be consistent with a shift to an SoC-like approach.
Additionally, Medfield includes a bridge between IOSF and the Open Core Protocol (OCP). The latter is an open, industry standard interface for connecting IP blocks, which was also used in the Langwell hub. Intel’s strategy around IOSF and OCP has not been fully articulated, so it is unclear which IP blocks will use which interconnect. The most likely explanation is that IOSF is tailored for IP that requires high performance (e.g. graphics and video) or comes from trusted partners. On the other hand, OCP is intended to create an interface available to all IP vendors, especially those that may not have the resources to work with and test an Intel-specific interface.
Shared 256KB SRAM
In addition to the 512KB L2 cache, Medfield also includes a separate 256KB chunk of SRAM that was not shown in Intel’s architectural diagram. To be clear, this is a specialized SRAM and not a cache. It is an always-on block that is used for a number of purposes in the system and optimized for the lowest leakage power, rather than the highest levels of performance. As one example, it is used by the ISP for holding image data.
More importantly, the SRAM holds architectural state during various power save modes. Just as the Saltwell core includes a C6 SRAM for storing the x86 state, this larger SRAM serves a similar purpose for the overall platform. When entering the S0ix states and shutting down SoC components such as the graphics or video codecs, the architectural state and configuration information will be retained to this 256KB SRAM.
The memory controller for Medfield has also received significant attention from Intel’s design team. The previous generation was limited to a single 32-bit channel of LPDDR1 at 400MT/s, which is significantly slower than almost every other SoC; or DDR2 at 800MT/s, which is too power hungry for mobile devices.
The new memory controller is an LPDDR2 design that is twice as fast, running at 800MT/s with 32 transactions outstanding. Medfield is also a dual channel design, so the maximum bandwidth is 6.4GB/s. Each channel can address 128-512MB of memory, with 4Gbit DRAMs.
However, not all versions will use both channels. Specifically, the dual channel memory interface is only available for versions where the memory and SoC are package-on-package (PoP) stacked. The height of the whole PoP is 1.4mm, while the unstacked version is 0.73mm. This is a fairly common approach, also employed by Qualcomm and TI. Incidentally, the main benefit of PoP is more compact board design. For LPDDR2, there is very little power savings, although there will be advantages for LPDDR3 and future interfaces.
Last, Medfield includes a large number of I/O interfaces. USB-OTG has been carried over from the previous generation and is connected through the external PMIC. MIPI-HSI connects to either an Infineon or third party wireless modem and a JTAG port is available for testing. There are also up to 89 GPIOs and an assortment of I2C, SPI and UARTs.
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