Notes on the Montecito Launch

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On Tuesday, I attended Intel’s launch for the eagerly awaited Itanium MPU known as Montecito. I was also given an opportunity to speak with Kirk Skaugen, the GM of the Server Platforms Group. While there has been pretty good coverage of the event, there has not been much in the way of analysis. Rather than rehashing old information, we will try and add some significant insight into the already familiar news.

In 2004, Paul DeMone wrote Sizing up the Super Heavyweights, an excellent article about Montecito, which gives a good picture of the processor, and its main competitor, the POWER5/5+ from IBM. The only substantially new developments since that article are that some aspects of Foxton have been disabled for unknown reasons. Foxton is a dynamic power measurement subsystem that was used to automatically adjust voltage and frequency based on power consumption; so an OEM could preset a Montecito device to operate at exactly 100W, or exactly 80W, what ever happens to fit in their power/thermal envelop. One advantage of Foxton technology is that since it dynamically adapts to power and heat requirements, MPUs can be binned more aggressively, without worrying about going over TDP or drawing too much power. However, since the frequency control element of Foxton have been turned off, Intel has been forced to bin much more conservatively. Instead of a 2GHz MPU, Montecito will top out at 1.6GHz. The whole respin process also delayed Montecito by a year, which weakened the position of some OEMs (especially SGI).

Intel’s Perspective on Itanium

The first thing that Intel is keen to emphasize is that Itanium is first and foremost targeted at the high-end of the market. Roughly 50% of server revenue and 10% of volume still belongs to mainframes, RISC/UNIX combinations and other proprietary systems. Although there are arguments as to the original intent of the architecture, Intel is currently gunning for the high-end with Itanium. To drive home that point, Intel has to some extent tried to ignore or marginalize x86 whenever discussing Itanium and emphasize the comparison against SPARC and PowerPC.

Positioning Itanium against SPARC and PPC is eminently logical, however omitting any references to x86 when discussing Itanium seems short-sighted. For the most part, x86 does not directly compete with Itanium, but acts as a substitute. Essentially, when x86 becomes ‘good enough’ for what the customer needs, they may shift if it is cost-effective (and it may not be in all circumstances). Currently, it looks like the strategic plan for IPF is to differentiate based on stability, scalability, RAS features, and also value added software and services from vendors. The real question is how long will these differentiators work; unfortunately, markets are defined by customers and what they look at, not by simple black and white diagrams with neat boxes. For Intel, clearly the goal is to use a combination of x86 and Itanium to squeeze competing vendors from below (with x86 substitution), and above, with competition from Itanium. However, without the proper marketing strategy, x86 will end up squeezing both Itanium and RISC competitors from the bottom.

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