PCMark 2002 CPU Tests (Integer)
First up are the PCMark2002 integer tests. Most reviewers show only the ‘Overall’ results for the CPU tests, but I think this doesn’t really give sufficient information to evaluate a processor properly. Let’s take a look at the individual results for the tests that are primarily focusing on integer performance…
As shown in the “PCMark2002 – A First Look” article referenced on the first page, the JPEG test fits into a fairly small cache (32KB, it would appear), so bus speed does not have any effect. The P6 and K7 based processors achieve almost identical scores, though the Tbird based K7 does show a slightly worse performance here. The P4 is fully 25% slower than the fastest chips, but this is likely because of the small L1 cache size. Notice that the Tbird Athlon is a bit slower in this test than the Tbred. Since this is not true for the Tualatin vs. Coppermine, it would appear that HW Data Prefetch does not help in this test, but the enhanced TLB in the Tbred has some impact.
The results from the “PCMark 2002 – A First Look” article shows that the Zlib Compression test is larger than 32KB, so cache size will definitely be a factor. We can see that effect here with the Morgan core Duron vs. the Tbred core Athlon – so the test is apparently larger than 192KB, but smaller than 256KB, as mentioned in the PCMark article. We can see that P4 does slightly better than the K7 core on this test when all things are ‘equal’ (small cache and slower bus). It is interesting to see how well the PIII performs in this test, even with an L1 cache that is smaller than K7. Is this because of the wider Backside Bus width of the Pentium III? It would appear that HW Data Prefetch has no impact here, but the enhanced TLB of the Tbred might have some impact.
The Zlib Decompression test shows something a bit different than the Compression test does. FSB speed seems to have some impact. This would indicate that the working set size is larger than 384KB, as it affects even the Tbird/Tbred cores. The large difference in results between the PIII T and Celeron T parts (as well as the Tbred/Morgan vs. Tbird parts) indicate that the HW Data Prefetch feature has a significant impact – much more for the PIII T than for the Tbred/Morgan cores. P4 still seems to be at a disadvantage, though not by nearly as much as in the JPEG test. Notice that the P4 matches or bests the CuMine PIII (without the Data Prefetch) at the same FSB. Here is one test where P4 seems to be better than the ‘original’ PIII, contrary to some reports that there is nothing P4 does better – but that is likely due to the HW Data Prefetch feature.
The P4 really shines in this test. In the article on HW Data Prefetch, this particular test looked to be highly influenced by that feature. The results here only seem to confirm that. What is very interesting is that the Morgan/Tbred parts do not exhibit the same performance improvement (though it is still significant), even though they too have Data Prefetch logic. This seems to indicate that the AMD implementation is significantly different than the Intel one. It is difficult to determine if the enhanced TLB of the Tbred/Morgan cores have any effect, but likely not, considering the nature of this test (scanning sequentially through memory)
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