MPF 2002 coverage – AMD Opteron

Many details about the AMD Opteron processor had been released previously. In order to avoid redundancy, we will simplify the coverage here, and only provide coverage for features and announcements that had not been discussed previously. In the second presentation of the PC servers session, Fred Weber from AMD released some preliminary SPEC scores for the AMD Opteron processor. Although these numbers must be classified as “estimated” to satisfy the strict disclosure requirements of the SPEC score submission protocol, Fred Weber claims that the numbers were indeed obtained on real hardware as it exists in AMD’s laboratory. The AMD Opteron, operating at a frequency of 2.0 GHz, and coupled with registered PC2700 DDR SDRAM memory achieves a SPEC int 2000 score of 1202, and a SPEC fp 2000 score of 1170. These numbers were obtained by using Intel compilers and the Opteron processor operating in 32 bit mode. Fred Weber claims that with compilers that can properly optimize for the AMD-64 bit architecture and take advantage of the additional architectural register available, upwards of 20% performance may be obtained for the same processor operating at the same frequency in 64 bit mode. The additional caveat that the 20% performance delta would be application dependent, and subject to the memory access patterns of the workload. For a workload that is CPU bound and has a heavy register pressure, the speedup of 20% may be observed. For a workload that is not similarly bound, and accesses memory frequently, the benefit of the additional architectural register is greatly lessened.

AMD also disclosed some impressed figures with respect to the memory latency characteristics of the DDR SDRAM memory system in the Opteron processors. While the peak memory bandwidth of the dual DDR SDRAM channels on the Opteron processor may be computed by simple arithmetic, the latency characteristics of memory accesses could not be similarly obtained from available DRAM datasheets. AMD disclosed that a memory access that hits in an open DRAM page would have a load-to-use latency of between 48 to 57 ns. Memory accesses that suffer a DRAM page miss would incur an additional access latency penalty on the order of 20 ns. This latency characteristic compares favorably to an open DRAM page access latency on the order of 100 ns for IA-32 systems with an offchip memory controller. The low latency also compares well against the EV7 processor with integrated RDRAM memory controllers. The memory access latency of the EV7 processor to an open RDRAM page has been previously disclosed to be 75 ns.

AMD has partnered with Newisys, a new startup from Austin, Texas, to provide a complete server solution for the AMD Opteron processor. In the photograph of the system board, we show the picture of a 1U server system board displayed by Newisys. Newisys claims that the 1U server system is ready for immediate shipment as soon as AMD releases the Opteron processor. In the photograph below, we also labeled several component of the dual Opteron 1U server. Under the heat sinks labeled as “1”, two 1.4 GHz Opteron processors sit peacefully running a sample workload, demonstration the functional operation of the 1U server system. We also labelled two module board as “2”, These module boards contain the power regulators for the respective Opteron processors. The digit “3” then indicates the location of the DDR SDRAM memory modules. The digit “4” then shows the location of the memory modules that provide appropriate termination for the dual DDR SDRAM memory channels.

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