The Myths and Realities of Overclocking

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The timing regularity provided by the processor clock is harnessed using a basic one-bit memory element known as a D-type flip-flop, as shown in Figure 2 (many microprocessor designs also employ a different element known as a transparent latch but the difference is immaterial for my explanation). The simplest D-type flip-flop, or D-flop, has a data input “D”, a clock input and a “Q” output. The D-flop acts like a camera that “takes a picture” of the value on the “D” input on each rising edge of the clock, and outputs that value on its “Q” output. However, this “camera” has a relatively long exposure time, so it is necessary for the D input to be unchanging for a short time before the rising clock edge (the setup time) and for a short time afterwards (the hold time). If the D input changes state within this sampling window, then the Q output of the flip-flop is undefined. In the worst case, the input is sampled at the razor’s edge of decision between a “0” or “1”, a condition known as metastability. In this state the Q output can linger between a “0” and “1” for a short period of time, which can cause problems because two different logic gates connected to Q may see opposite logic values. Other than this short sampling window, the flip-flop is indifferent to the value on its “D” input and will continue to drive the last captured value out on the Q output. These insensitive regions are shown in Figure 2 as gray bars in the D input waveform. On the rising edge of the clock marked “E1”, the D input is sampled as a “0” and after a short delay (known as the clock to output delay) the Q output changes to a “0′. Similarly, on the clock edge “E2” D is sampled as “1” and Q changes to a “1”

The circuitry in a microprocessor is designed as synchronous logic organized into state machines and functional pipelines. Finite state machines are used in microprocessors to implement the instruction decode and execute control logic, counters, as well as interface functions like the system bus protocol. A typical finite state machine is shown in 3. A set of flip-flops is used to store the current state variables Si. The value of the current state, as well as control inputs, Ij, act as the inputs to a block of combinational logic (a network of basic logic gates like AND, OR, NAND etc. which act as a lookup table) whose outputs, Ni, feed to the D inputs of the state variable flip-flops. Every clock cycle, the state machine either stays in its current state or advances to a different state depending only on its current state and the value of the inputs.

Microprocessors typically process instructions and compute results using synchronous functional pipeline logic. The basic arrangement of one stage synchronous pipelined logic is shown in Figure 4. In a synchronous functional pipeline the instruction information and data advance from pipeline register “N” to pipeline register “N+1” on every rising clock edge. Each stage consists of a block of combinational logic such as a decoder or arithmetic logic unit (ALU) that sits between two sets of pipeline registers.

In figure 4 the output of pipeline stage “N” are the values Ai. These values are the input to the combinational logic, which in turn generates the values Xj. On the next rising clock edge the output of the “N+1” pipeline register changes to the value of the Xj inputs generated during the previous clock period.


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