The maximum clock speed that a synchronous circuit like the finite state machine or functional pipeline can operate is limited by the sum of the following time intervals, which must total less than or equal to one complete clock period:
- the clock to output delay of the originating flip-flops
- the maximum propagation delay (input to output delay) of the synchronous logic, and
- the setup time needed by the receiving flip-flops.
These constraints are shown in Figure 5. There are other factors involved, such as clock skew, but these aren’t relevant to this discussion.
If the clock period is greater than the sum of these three factors then the synchronous logic is operating below its maximum clock rate (i.e. has timing “slack”). If the slowest input to a flip-flop is arriving with just enough set up time for proper operation the circuit is operating at the maximum clock rate. If the clock rate is above the maximum clock rate then one or more input to a flip-flop may arrive too late to be successfully latched. If this happens in a finite state machine, then the microprocessor might erroneously update its program counter, miss or repeat a processing step in the execution of an instruction, or violate its bus interface protocol.
If the timing violation occurs in pipelined functional logic then an incorrect result may be registered for the current instruction. In a complex system like a modern microprocessor there are many tens or hundreds of finite state machines and multiple functional pipelines. The maximum clock rate of the microprocessor is set by the slowest path between two flip-flops anywhere on the chip. The slowest path is called the critical path.
The propagation delay of the logic gates on the critical path varies from part to part and also changes depending on the power supply voltage and the chip temperature. The part-to-part speed differences occurs due to small variations in transistor characteristics, such as gate length and gate oxide thickness, that occur during wafer fabrication and are essentially fixed for the lifetime of the device. The manufacturing variations in gate delay are the reason why microprocessors built in the same technology are offered in a variety of speed grades. The chip’s power supply voltage and operating temperature will also affect the logic propagation time. Increasing the temperature or reducing the supply voltage will increase gate delays and reduce the maximum clock frequency. Typical gate delay variation with voltage and temperature for a CMOS process are shown in Figure 6.
Notice that CMOS chips run fastest at low temperatures and high power supply voltage and slowest at high temperatures and low supply voltage. It is important to note that the temperature in Figure 6 refers to the junction temperature, that is the temperature within the integrated circuit transistors. It is not uncommon for the external temperature of the package of a high power chip like a microprocessor to be tens of degrees higher than the ambient air temperature within a computer case. The temperature on the chip die can be easily be tens of degrees higher than that at the surface of the package.
Now, these relationships between logic gate delay time and supply voltage and device operating temperatures are not just theoretical. Supply voltage and temperature directly affect how fast a microprocessor can be clocked and still operate correctly. In fact when a new microprocessor is developed, or an old one is shrunk into a new process, engineers will characterize (carefully test a large group of samples of) the part to determine how fast the MPU can operate changes when the supply voltage and temperature change. In Figure 7 is something called a shmoo plot for an individual sample of the 0.2 mm Motorola G4 PowerPC microprocessor (data from an ISSCC 1999 paper). This shmoo plot is a two dimensional plot that indicates whether the sample device operates correctly (pass) or is being clocked too fast (fail) for the combination of clock frequency (x-axis) and power supply voltage (y-axis).
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