The PWRficient Family
From the beginning, P.A. focused on developing a family of products that is extensible and scalable. This required a lot of upfront investment and design time to ensure that their efforts would be reusable. They hope that by extensively reusing their IP, that they can tape out and productize their designs much more rapidly; the stated goal was a 3 month tape out, once the first core had been developed. This shorter development time would allow them to address more markets than would be otherwise possible. The PWRficient family incorporates three elements that we will explore in this article:
- The PA6T processor core
- The CONEXIUM interchange
- The ENVOI I/O system and offload engines
Together, these three elements form a potent platform that only needs DRAMs to be complete. Moreover, each element can be scaled in a variety of dimensions to accommodate various markets and price points. Figure 1 below is a marketing diagram that shows some of the scalable factors in the PWRficient family.
Figure 1 – Scalability of the PWRficient Family (from a P.A. Semi presentation)
The initial implementation is depicted below in Figure 2 and is expected to sample in the third quarter of 2006. It is implemented in a 65nm process and is expected to run at 2GHz, using up to 1.1V and dissipating 25W maximum and 13W typical.
Figure 2 – PA-1682M System on a Chip (modified from a P.A. Semi presentation)
As the brand name indicates, the underlying theme is power efficiency, so the analysis of a given feature always involves the performance gain, and the power or heat cost.