Power delivery is one of the most significant challenges in modern processors. The power delivery network (PDN) must meet the demanding requirements of modern CMOS technology, supply power with excellent efficiency, and swiftly respond to changes in power draw.
These problems hold for 1W smartphones up to 200W server processors and massive machine learning accelerators like Cerebras’ 15kW wafer-scale CS-1. To run at the target clock frequency every transistor and circuit in a modern chip requires power supplied at the right voltage. If the supply voltage is too low the circuits will switch slowly and fail – producing incorrect results, stability problems, and other peculiar failures .
Generally, CMOS logic tends to operate at around 1V due to the physics of silicon. However, modern process technologies using FinFET transistors and other techniques have nominal voltages between 0.65V and 1.2V. Innovative circuit designs can use a supply voltage that is close to the transistor threshold voltage, a technique demonstrated by Intel’s near-threshold voltage research. While processors using NTV (e.g., Ambiq Micro) recently entered production, it is generally quite novel. The power consumption of a switching circuit (such as a processor) is proportional to the square of the voltage, so reducing the voltage is critical for boosting efficiency. For chip designers this is a classic Goldilocks problem: the voltage should be just high enough to avoid errors and no greater.
However, low voltage operation is a challenge for power delivery because it requires delivering large currents to the processor. Take a modern server processor like Intel’s 14nm Cascade Lake Xeons. High-end Xeons have a TDP of 205W, which conceptually translates into a current of 205A at 1V. In reality processors are far more complex and have many different voltage domains and power supplies, but a simpler example is useful. Keeping the power consumption the same and reducing the voltage to 0.75V would increase the current required to 274A . While Intel’s high-end server processors are fairly power-hungry, they are easier to deal with than some accelerators. For example, Nvidia’s Volta V100 is rated for 450W, some future processors are expected to hit 600W, and as mentioned, Cerebras’ CS-1 is an astounding 15kW.
Generally, when transmitting power it is much more efficient to use a high voltage and a low current. At higher voltage the current is lower and fewer wires are needed to transmit power, which reduces costs. Additionally, the resistive losses are proportional to the square of the current, so increasing the voltage and reducing the current will reduce resistive losses and improve energy efficiency. This is the reason why long distance power lines typically operate above 110kV, and the same general concepts apply within a server or data center. While some servers use traditional 12V power supply, some newer designs use 48V for efficiency – and this is particularly common for high-power accelerators that draw over 350W.
Putting these factors together, the conceptual goal of power delivery is to move power throughout the system at as a high a voltage as realistic for transmission efficiency, and then convert down to a very low and stable voltage for efficient and correct computation.