Power Delivery in a Modern Processor

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Swift Responses Needed to Dynamic Conditions

The speed of the FIVR hints at one of the biggest challenges in power delivery for modern processors. Focusing on steady-state power and thermal characteristics (e.g., TDP) understates the magnitude of the power delivery problem. Modern processors are extremely dynamic and their behavior changes based on the workload. When a transistor switches, it requires a relatively small amount of current. However, if many transistors switch simultaneously the total current draw can become significant and create noise on the on-chip power supply. In high-speed designs like a CPU or GPU, the number of transistors switching can change dramatically from cycle to cycle. For example, when a CPU core starts executing AVX512 multiply-accumulate operations, the power draw is much greater than simply executing integer arithmetic. Similarly, dynamic voltage and frequency scaling systems (DVFS) will change the processor frequency and voltage on the fly in response to changes in the workload or operating conditions. These sudden spikes in current draw can cause the voltage to temporarily dip (referred to as a droop).

Two examples help to illustrate this challenge. Most data centers are optimized for efficiency and high utilization – which translates into 40-60% CPU utilization for the processor, with bursts that go even higher. Returning to the 205W TDP Intel Xeon datasheet, the processor is rated for a maximum current draw of 273.75A across the major voltage rails and an incredible 413W power draw at the package level to deal with peak demand.

Client processors, especially for notebooks and smartphones are an entirely different story, and even more challenging. They are typically optimized for very burst behavior and must deliver maximum performance for short periods of time (e.g., loading a webpage), while drawing practically no power during idle (e.g., waiting for user input). A notebook that is operating at 40-60% CPU utilization would have a tremendously short battery life and a client processor probably spends about 90% of its time at idle. The overall result is that client processors have an even greater discrepancy between the TDP and maximum power and current draw. The most recent Ice Lake U-series and Y-series processors are rated for 15W and 9W TDP. To deliver greater performance, system vendors can configure the TDP as high as 25W and 12W respectively. However, the maximum rated current draw for the CPU and GPU is dramatically higher – up to 70A and 49A respectively, and this excludes the power for the memory controller and system agent.

The crux of the challenge is that voltage regulators, whether motherboard VRMs or Intel’s FIVR, are much slower than the transient current spikes caused by switching activity. The Haswell FIVR can ramp up a power rail (e.g., to a core) from 0V to 0.8V in about 0.32 microseconds. However, for a modern 3GHz design, that translates into roughly 1000 clock cycles. Slower conventional VRMs can increase the voltage at about 10-25mV per microsecond, and would take around 100X longer to make a similar ramp from 0V to 0.8V, or about 100K clock cycles. Without proper design, these transient spikes can effectively cause a voltage droop and brown-out, conceptually similar to how in older homes the lights dim when a microwave or hair-dryer starts. As an aside, Skylake client processors and AMD processors use an on-die low-dropout (LDO) voltage regulator that is also very fast. However, LDOs act as a variable strength resistor and only reduce voltage to a power rail. Because LDOs operate through resistance, they tend to be inefficient for larger changes in voltage (E.g., >10% voltage reduction).

As discussed previously, if a processor is operating at 3GHz and the voltage suddenly drops then the transistors may no longer correctly function, so either the voltage must be kept constant or the frequency must drop. In practice, most companies employ a combination of several techniques. For example, AMD developed an adaptive clocking technique that reduces the frequency during some voltage droops.

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