System Power Delivery Balances Performance, Efficiency and Cost
Power delivery for high-performance processors must navigate myriad challenges. Ideally, the power delivery network primarily operates at very high voltage for transmission efficiency, but ultimately provides a low and stable supply voltage to the CMOS logic that implements the processor. The power conversion, from AC to DC and from high-voltage to low-voltage should be as efficient as possible.
At the same time, the current required by the processor is changing constantly in response to dynamic conditions such as the mix of instructions or the DVFS system. To buffer against these near instantaneous changes and reduce power supply noise, modern designs use decoupling capacitors at nearly every level of the power delivery network from the motherboard to the processor die itself. Faster and more responsive power delivery networks require less decoupling capacitance. Zooming into the processor itself, there are a number of on-die capacitor options. The simplest is using regular transistors, which are easy to place and work on any process technology but are fairly inefficient. However, many semiconductor manufacturers also offer superior capacitors built with special process technologies or circuit designs such as MIM capacitors in the metal layers and less commonly, deep trench capacitors in the silicon or interposer substrate.
These variables are all related: process technology, decoupling capacitors, DVFS systems, voltage regulators, etc. and processor designers must account for all of them to deliver the best performance, efficiency, and cost.