A Big Blue Shadow over Alpha, SPARC, and IA-64

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Big Iron Means Big Bandwidth

Despite the impressive clock rate the POWER4 will achieve, it seems likely that even faster clocking x86 processors will already be on many desktops when the first IBM servers using the new MPU ship in the second half of 2001. What is so special about designs like POWER4 and the upcoming Alpha EV7? Why would a server or workstation builder pay an order of magnitude more for a slower clocking ’boutique’ microprocessor?

It is true that the floating-point performance of these RISC powerhouses is much higher, but the amazing leveling power of Moore’s Law means PC processors will catch up to a given leading edge RISC design in FP performance in only 3 or 4 years at most. The 1.0 GHz Athlon box at your local department store can do better on SPECfp95 than a 600 MHz top of the line Alpha EV56 based workstation that represented the pinnacle of personal computing for the power user a little over 2 years ago.

The primary characteristic that separate servers and workstations from PCs is bandwidth. By historical computing standards the contemporary PC is an appallingly unbalanced system. Like a idiot savant borne of silicon, a computer enthusiast’s x86 based PC has integer CPU performance capable of putting a modern mainframe to shame and 3D imaging capability not too far removed from a low end SGI workstation. But its relative I/O and memory bandwidth is ridiculously low for most classical commercial and technical computer applications. An illustration of how future server processors will offer much higher bandwidth is shown in Table 1.

Unit

Pentium III

Pentium IV

POWER4

Alpha EV7

Clock Frequency

GHz

1.00

1.50

1.50

1.25

Peak Execution Rate

BIPS

3.0

4.5

2 x 7.5

5.0

Data cache Bandwidth

GB/s

16

48

2 x 36

20

L2 cache Bandwidth

GB/s

16

48

144

20

L3 cache Bandwidth

GB/s

16

Peak Sys Bandwidth

GB/s

1.1

3.2

Peak Mem Bandwidth

GB/s

8

12.8

Peak I/O Bandwidth

GB/s

84

28.8


Table 1 Bandwidth of Future PC and Server MPUs

Future PC processors will continue to offer tremendous computational capacity and enormous on-chip cache bandwidth relative to future server MPUs. But the disparity between PC processors and server processors in off-chip bandwidth will greatly increase. The Pentium IV will triple its system bus bandwidth over the previous generation Pentium III. But this relatively limited bandwidth must be divided between accesses to main memory and all I/O devices in the system including the graphics display. In contrast, the POWER4 and EV7 will integrate the main memory controller on-chip and offer both huge memory bandwidth and I/O and inter-processor communications bandwidth. This new generation of server processors is designed to allow significant SMP systems to be built while reducing the effects of traditional bottlenecks that limit performance scaling.


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