An Overview of High Frequency Processor-System Interconnects

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This is the first installment in a two part article about the IBM Elastic I/O interconnect for the PPC970, presented at MPF 2002. This first piece examines the physical specifications for the Elastic I/O interconnect, while the second will deal with the protocol that drives the interconnect.


In the recent Microprocessor Forum, IBM released preliminary details about its upcoming PowerPC processor, the PowerPC 970. The PowerPC 970 processor is targetted at the high performance desktop, workstation and low-end server markets, and inherits much of its technical heritage from the server oriented POWER4 processor. One of the most interesting aspects of the PowerPC 970 processor is the high frequency and high bandwidth processor interconnect planned for this processor by IBM. In Figure 1, we show a diagram of the PowerPC 970 processor connected to its companion chip via the high frequency Elastic I/O interconnect.

Figure 1: Elastic I/O interconnect of the PowerPC 970 processor

Figure 1 shows the basic details of the Elastic I/O on the PowerPC 970 processor as announced by IBM. The Elastic I/O operates at an integer fraction of the CPU core frequency. In this case, the Elastic I/O operates at 1/2 of the frequency of the CPU core, and for the 1.8 GHz version of the PowerPC 970 CPU, the Elastic I/O would operate at a frequency of 900 MHz. The Elastic I/O consists of two unidirectional point-to-point interconnects that is 4-byte wide in each direction. Simple arithmetic reveals that the Elastic I/O could support a raw bandwidth of 3.6 GB per second in each direction. However, unlike more traditional processor busses with separate address, command, control and data channels, the address, command and data bits for each and every transaction request are all directed onto the same set of wires. As a result, the cycles devoted to the transmission of the address and command requests must be subtracted out in a computation of the available data bandwidth of the Elastic I/O interface. In the PowerPC 970 presentation, IBM claims a peak data bandwidth of 6.4 GB per second from the raw bandwidth of 7.2 GB per second. The Elastic I/O interface of the PowerPC 970 processor also includes some separate control signals that allow the companion chip and CPU to communicate cache snoop acknowledgment and response without occupying the full width of the 32 bit wide Elastic I/O channels.

In this article, we will attempt to cover some of the basic concepts that enable the 900 MHz operation of the Elastic I/O connection interface. We will also make references to other more classical processor interconnects such as Intel processor busses and the Alpha EV6 processor interconnect found on Alpha EV6 and AMD Athlon processors.

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