An Overview of High Frequency Processor-System Interconnects

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Bus Basics

What is a Bus?

In Figure 2, we show four basic combinations of uni-directional, bi-directional, point-to-point and multi-drop bus interconnects.


Figure 2: Uni-Directional and Bi-Directional Point to Point Connections and Multi-Drop Busses

The Elastic I/O used by IBM in the PowerPC 970 processor is a uni-directional point to point interconnect, and signals only travel in one direction, with drivers on one end of the interconnects, and receivers on the other end of the interconnects. The data channel of the Alpha EV6 processor bus interconnect uses a bi-directional point to point interconnect, and a signal may be driven from point A to point B or from point B to point A depending on the dynamic requirement of the data flow between the processor and the support chipset. Finally, Intel processors such as the venerable Pentium !!!, Pentium 4, Xeon, and Itanium series of processors use the more traditional multi-drop bus. In this configuration, each processor can potentially drive signals onto the bus, and when one agent on the bus drives the bus, all of the other agents on the bus can observe the signals as asserted by the driving agent.

In general, multi-drop busses are more difficult to push to higher clock frequencies, but they are capable of supporting small-scale SMP configurations at a lower cost of pin count. Note: While topology has a contributing effect on the operating frequency of the interconnection scheme, it is not the sole limiting factor. Signaling technology and protocol are also important factors that determine the limits of operating frequency.


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