An Overview of High Frequency Processor-System Interconnects

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Bus Limitations

System Bus Frequency Also Depends on Signaling Technology

There are numerous types or classes of electrical signaling technology: TTL, ECL, RSL, SSTL, Rambus Yellowstone, GTL+, AGTL+ and others. There are a large number of signaling technology, some designed for high frequency, some designed for lower power consumption, while still others exist to maintain compatibility with legacy electronic devices. In Figure 7, we show a basic signaling technology where two different voltage levels are used to represent two different logic levels.


Figure 7: Signaling Technology in a Nutshell

When a single bit of information is to be transmitted from one end of the signal interconnect to the other end of the signal interconnect, the voltage level on the interconnect is made to switch state from one state to another. The voltage switches state, shown in figure 7 as a certain magnitude of voltage swing in a finite amount of time. The change in voltage divided by the time required for the state switch is known as the slew rate of the voltage swing. Since the slew rate cannot often be increased to facilitate a faster state transition, the alternative is to reduce the magnitude of the voltage swing between the voltage states. For this reason, the high frequency signaling technologies all have very small voltage swings between logic states.

There are many different signaling technologies, and the exacting details are too numerous for this brief overview. We will thereby simply assert that the speed of signal propagation and logic state switch on the system interconnect depends not just on the characteristic impedance of the system interconnect and the number of loads on that interconnect, but also the signaling technology. We will hereafter assume a “generic” binary signaling technology not unlike SSTL or RSL.

If You Send the Signals in Parallel, Across Parallel Interconnects, Will They Reach Destination at Same Time?

In figure 8, we show a two poorly matched signal interconnects on a parallel bus. In this figure, we show that it takes longer for the signals from the driver to reach load B as compared with load A. Moreover, we also show that path #2 to load A is longer than path #1 to load A. As a result, the difference in the physical trace lengths could introduce timing skew between signals sent on path #1 and path #2. In such a case, even if signals are sent from the driver at the exact same instance in time, they will not arrive at the interface of the load at exactly the same instance in time.


Figure 8: Differences in Trace Lengths and Impedance Characteristics Introduce Skew

Ever Wonder Why Traces have to Snake Around?

Differences in Path lengths force system designers to go to heroic efforts to match the lengths of the traces of a parallel bus. Most any modern system boards will have more than a few signal lines that snake around parts of the board to attempt to match signal path lengths.


Figure 9: System Board Designers Try Hard to Path Length Match Wires in Parallel Busses

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