An Overview of High Frequency Processor-System Interconnects

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Skew Troubles

Wider Busses Tend to have Terrible Skew Characteristics

In figure 10, we extend the ideas expressed in figure 8 and figure 9, and show that signals in a parallel bus often show varying amounts of skew.


Figure 10: Wide Parallel Busses Generally Show Widely Varying Skew Characteristics

Modern parallel busses that do not have de-skewing circuitry for individual bits must account for the worse case skew differential. In a high frequency interconnect, skew differential contributes heavily to limiting the operating frequency of the parallel system interconnect. For high frequency parallel signaling across a system board, signal de-skewing is an important and necessary aspect of the design. There are two important aspects to the signal-skewing problem. One aspect of the problem is that signal skew may be introduced by static variables, such as signal path lengths, or mismatched impedance characteristics. The second aspect of the problem is that there is a dynamic component to the signal skew that varies with the environmental conditions of the source chip, the destination chip, as well as the transmission line itself. The dynamic portion of the skew equation is a function of component variances that is introduced by a change in temperature or voltage. The existence of the dynamic component of the skew equation means that for extremely high frequency designs, circuits deployed to de-skew signals on a parallel system interconnect may have to be dynamically re-calibrated during runtime to ensure that the signal skews are properly compensated for, regardless of the changes in the operating environment. (Minute differences in component characteristics between a cold boot up and a warm runtime can introduce skew differentials in a high frequency parallel system interconnect)

Elastic I/O Designed to Handle Skew

In figure 11, we show that the parallel interconnect actually has a few signal paths that were different in length.


Figure 11: Elastic I/O Designed to Tolerate Skew

IBM’s Elastic I/O, as presented in the 1999 Hotchips conference, has been designed to tolerate a large degree of variance between the characteristics of individual signal paths. In this case, we show some intermediate signal lines in the parallel interconnect as having longer path lengths to avoid obstacles in the system board. Furthermore, with properly matched impedances on the interconnects, a driver can begin to place additional bits onto the interconnect even before the previous bits reach the destination. As mentioned previously, this feature must rely on proper matching of the load impedance with the characteristic impedance of the transmission line. In the POWER4 processor, the Elastic I/O runs at 500 MHz, and it is used as a high frequency chip to chip interconnect between the different CPU dies. In the PowerPC 970 processor, the high frequency system interconnect is tie to the companion chip that contains the memory controller that performs the memory access functionalities for the PowerPC 970 processor.


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