An Overview of High Frequency Processor-System Interconnects

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SMP Issues

Dedicated Ports are Needed For SMP Configuration

In a shared memory multi-processor configuration, the companion chip (system controller) must explicitly broadcast cache snoop requests to each CPU, and collect snoop responses from each CPU. Unlike processors connected in a shared bus topology, where addresses for snoop requests can be effectively broadcast through the shared bus, processors connected by point to point connection fabrics must rely on the support chipset to rebroadcast snoop addresses and accept snoop results for the maintenance of cache coherency. In this manner, the point to point “processor bus” found on the PowerPC 970 processor is not unlike the Alpha EV6 “processor bus”. However, unlike the connection scheme on the PowerPC 970 CPU, the Alpha EV6 bus use separate channels for data and command+address. The data bus found on the EV6 bus is bi-directional, and must be directed properly for transaction read and writes.

Figure 12: For Point to Point Connections, Each CPU Needs Dedicated Port in SMP Configuration

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