In this article, we briefly examined the connection scheme found on the Power4 processor. We expressed in abstraction some reasons why a unidirectional point to point connection scheme can be pushed to higher frequencies as compared to a bi-directional multi-drop bus based connection scheme, even when using comparable signaling technology. Furthermore, we also examined problems associated with signal skews on a high frequency and wide parallel interconnect, and how the PowerPC 970 processor would benefit from its POWER4 lineage in inheriting a high frequency, low point count, wave pipelined interconnect with built-in de-skewing circuitry.
 Dally, W. “Digital System Engineering Lecture notes”, Stanford
 RIMM Module Propagation Delay Measurement and Optimization, Rambus Inc.
 Ferraiolo, F., Cordero E., Dreps D., Floyd M., Gower K., McCredie B.,
“POWER4: Synchronous Wave-Pipelined Interface”. Presented at Hotchips
 Poulton, J., “Signaling in High Performance Memory Systems”,
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