An Overview of High Frequency Processor-System Interconnects

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In this article, we briefly examined the connection scheme found on the Power4 processor. We expressed in abstraction some reasons why a unidirectional point to point connection scheme can be pushed to higher frequencies as compared to a bi-directional multi-drop bus based connection scheme, even when using comparable signaling technology. Furthermore, we also examined problems associated with signal skews on a high frequency and wide parallel interconnect, and how the PowerPC 970 processor would benefit from its POWER4 lineage in inheriting a high frequency, low point count, wave pipelined interconnect with built-in de-skewing circuitry.


[1] Dally, W. “Digital System Engineering Lecture notes”, Stanford University.

[2] RIMM Module Propagation Delay Measurement and Optimization, Rambus Inc.

[3] Ferraiolo, F., Cordero E., Dreps D., Floyd M., Gower K., McCredie B., “POWER4: Synchronous Wave-Pipelined Interface”. Presented at Hotchips 1999.

[4] Poulton, J., “Signaling in High Performance Memory Systems”, ISSCC 1999.

<b>Interconnection Schemes for Memory Systems</b>
In this article, we examined some differences between a point-to-point connection scheme versus a multi-drop bus based connection scheme. One fact that may be of interest to the reader is the fact that the discussion contained herein is not specifically limited to processor and chipset interconnects, but are also applicable to connection schemes seen in modern memory systems. Traditional memory systems such as DDR SDRAM that allow end users to upgrade the size of the memory system have the disadvantage that each memory module interface is a discontinuity on the transmission line. The discontinuities increase signal switching times and limits system operating frequencies. Ironically, non-expandable memory systems such as those found on high end graphics cards, especially those that have relatively smaller requirement for memory capacity, can operate a single rank of memory at a higher frequency, and could provide higher bandwidth as a result. The reason for this apparent paradox is that for these embedded memory systems, the signal traces are often very short and since there is only one single rank of memory chips, the connection closely resembles a point-to-point connection. As a result, the operating frequency of a tightly coupled and small memory system can be increased to a higher degree as compared to the operating frequency of a larger, user upgradeable memory system. In the not-so-distance future, we may see the onset of on-CPU memory controllers that is limited to the control of a single rank of non-expandable memory directly soldered to the CPU. A secondary memory controller may also exist on-CPU or elsewhere, but relegated to controlling a larger, slower, but user upgradeable memory system.

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