Off the RIMM: Nothing but Nets
The organization of signal flow within representative SDRAM and DRDRAM based memory systems are shown in Figure 1. The data path to the SDRAM memory is 64 bits wide and connect directly to up to four DIMM sockets using LVTTL level signaling. The SDRAMs within each DIMM are connected in parallel to the 64-bit datapath. This imposes a minimum granularity requirement of sixteen 4-bit wide SDRAMs, eight 8-bit wide SDRAMs, or four 16-bit wide SDRAMs within a DIMM.
All of the memory chips are generally located within a 3 or 4 inches of the memory controller ASIC, which limits signal propagation times. Usually up to four DIMMs can be supported on a single unbuffered SDRAM channel. The peak bandwidth is 64-bits x 100 Mbps or 800 MB/s. In addition to the 64-bit datapath, the memory controller has to drive a multiplexed row and column address to the SDRAMs along with control signals. Often, duplicate multiple copies of the address and control signals must be provided by the memory controller ASIC to control fanout and reduce output delays.
In contrast, the Direct Rambus memory system is arranged logically as a single long strip of DRDRAMs consisting of up to 3 RIMMs and 32 devices per channel. A common 16-bit wide datapath serpentines around the motherboard, entering and exiting each RIMM in the system until finally being terminated. A parallel termination resistor is needed for every high speed signal both to prevent transmission line reflections and to serve as a load for the switched current source Rambus signaling level (RSL) output buffer.
Note that the Rambus memory system will not function if any of the RIMM sockets are empty. This is remedied by the use of a special continuity module in the one or two of the maximum three RIMM sockets that might otherwise be left unoccupied. The continuity module is essentially a RIMM printed circuit board without any DRDRAMs on it. Since both DRDRAMs and the channel are 16-bits wide, the granularity is excellent – a RIMM with a single DRDRAM on it would function at full system bandwidth (16-bits x 800 Mbps = 1600 MB/s peak). This points to an important advantage of Direct Rambus over SDRAM – twice the peak bandwidth yet only about one third as many memory controller ASIC I/O signals are needed.
A Tale of Two Clocks
It is said that a man with one clock always knows the time but a man with two clocks is never sure. In the case of Direct Rambus the dual clock timing generation scheme is its most elegant and clever feature. As shown in Figure 2, the 400 MHz clock (whose rising and falling edges are used to synchronize data transfers within an 800 Mbps Direct Rambus memory system) is generated by a special clock generator chip located just beyond the farthest RIMM slot. This differential clock is threaded through the three RIMMs and/or continuity modules in the direction of the memory controller ASIC. On the way it connects to each DRDRAM memory device’s CTM or “Clock To Master” input pin. When this clock reaches the single input pin at the ASIC, the signal trace on the motherboard is bent around 180 degrees and sent back through the three RIMMs again before finally being parallel terminated. On the second, outward trip through the RIMMs, the clock trace is connected to each DRDRAM’s.cfm or “Clock From Master” input pin.
When the memory controller sends a command, address, or write data packet to a selected DRDRAM it clocks it out using its input clock. In turn, the selected DRDRAM device uses its.cfm clock input (delayed by 90 degrees) to sample the received command, address, or write data packet. Notice that the clock propagates along the outward leg to the selected device’s.cfm pin in the same direction as the packet from the controller. This means that the clock will tend to “track” the packet as it travels from the controller to the target DRDRAM and allow accurate sampling. For a read command, the selected DRDRAM transmits its output data using its CTM clock input. In this case, the read data heading towards the memory controller ASIC is tracked by the Rambus clock traveling on its inward leg.
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