Direct Rambus Memory, Part 1 – The Basics

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How Fast Does Your Signal Fly?

Most people tend to think that electrical signals travel through wires virtually instantaneously. In reality, a electrical signal travels slower than the speed of light. In the case of a signal trace on an outside layer of a printed circuit card (“microstrip”) made out of FR10 fiberglass, it travels at a rate of about 1.8 ns per foot (light in a vacuum takes about 1 ns to travel one foot). For an inner PCB trace sandwiched between two ground planes (“stripline”), the signal “slows down” to around 2.3 ns per foot.These figures are for an unloaded trace, i.e. no chips connected along the middle.

In the case of a Rambus channel there are up to 32 DRDRAMs connected to each signal. The distributed parasitic input capacitance of 32 memory chips will increase signal propagation delays by about 65% for outer traces and 50% for inner traces. In addition, Direct Rambus signals pass through multiple RIMM connectors whose slight imperfections and impedance mismatches can also slow down signal propagation.

These delays become significant when you realize that the farthest DRAM can be more than a foot away from the memory controller ASIC and the all-important read operation involves a round trip. That is, a command/address packet propagates to the farthest DRDRAM to initiate the read and then the data has to wind its way back to the controller. In this example shown in Figure 3, all the Rambus signals are assumed to be on microstrip traces. Round trip time-of-flight delay between the closest DRDRAM (green) and the memory controller ASIC (blue) is about 1.4 ns. In the case of the farthest DRDRAM (red) in a three RIMM system, the round trip delay is about 7.8 ns. This is quite remarkable when you consider that a DRDRAM can transmit a data bit every 1.25 ns. That means the farthest DRDRAM can pump more than three complete 16-bit words of data into the Direct Rambus channel wires before the first word arrives at the memory controller!

To put the “random access” back into a DRDRAM-based memory system, Rambus Inc. designed into each memory chip the capability of delaying the output of read data onto the channel beyond the normal 20 ns page read access latency by a programmed amount of 2.5, 5.0, 7.5, or 10.0 ns using the TPARM control register. When a DRDRAM-based computer system is powered-on or reset, the processor and memory controller ASIC perform an elaborate initialization ritual for each DRDRAM in the system. As part of this effort the read round trip delay for each memory device is measured and the longest delay is determined. Then the processor and/or ASIC attempt to equalize the round trip read access time for all devices by programming extra read delays into DRDRAMs closest to the ASIC. The net result is all DRDRAM devices appear as equally slow as the farthest device.

This scheme is illustrated using space-time diagrams in Figure 4. For the closest DRDRAM the signal time-of-flight (represented by the diagonal arrows) is minimal so the read access delay within the memory is set higher by 7.5 ns. For the farthest memory, the signal time-of-flight is more significant and the read access delay is the minimum value of 20 ns. Note that due to the 2.5 ns delay adjustment resolution the net round trip read latencies for the two extreme devices are not shown as identical.

Yet these delays have to be very nearly identical to attain reliable back to back read data bursting from two different DRDRAMs. This is like merging your car onto a busy highway when there is only a single car length gap in the traffic to exploit – your timing is critical. The secret to how this works is the fact that the precise read access time for each DRDRAM will vary slightly from location to location due to the differing phase relationship between the CTM and.cfm clocks as a function of distance from the memory controller. Somewhere between the time a read command is sampled into the selected memory device using the.cfm clock and read data is clocked out using CTM, there is a timing domain changeover which accomplishes the fine adjustment in latency to establish timing continuity along the whole length of the Direct Rambus channel.


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