RISC vs. CISC Still Matters

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When RISC processors first appeared on the scene most CISC processors were microcoded monsters with relatively little instruction execution pipelining. Processors like the VAX, the 68020, and the Intel i386 for the most part processed only one instruction at a time and took, on the average, five to ten clock cycles to execute each one. The first RISC processors were fully pipelined, typically with five stages, and averaged between 1.3 and 2.0 clock cycles to execute an instruction. RISC-based microprocessors typically were more compact and had fewer transistors (no microcode) than their CISC counterparts, and could execute at higher clock rates. Although programs compiled for RISC architectures often needed to execute more native instructions to accomplish the same work, because of the large disparity in CPI (clocks per instruction), and higher clock rates, the RISC processors offered two to three times more performance. In Table 1 is a case study comparison of an x86 and RISC processor of the early RISC era (1987).

Table 1 Case Study 1: Comparison of the Intel i386 and MIPS R2000 (1987)
&nbspIntel i386DXMIPS R2000
Technology1.5 um CMOS2.0 um CMOS
Die Size103 mm280 mm2
Transistors275,000115,000
Package132 CPGA144 CPGA
Power (Watts)3.03.0
Clock Rate (MHz)1616
Dhrystone MIPs5.7 113.9 2
SPECmark892.2 110.1 2
Note1 with 64 Kbyte external cache2 with 32 Kbyte external cache

In case study 1 the huge advantage of the RISC design concept for the upcoming era of VLSI-based microprocessors is clear. The MIPS R2000 processor is a smaller device built in an older semiconductor process with less than half the number of transistors as the Intel i386DX, yet it blows its CISC counterpart right out of the water in performance: more than twice the Dhrystone MIPS rating and more than four times the SPECmark89 performance (even with a smaller external cache).

The Empire Strikes Back

As can be imagined, the emergence of RISC, with its twin promises of simpler processor design and higher performance, had an energizing effect on the computer and microprocessor industry. The first CISC casualties of the RISC era, unsurprisingly, were in the computer markets most sensitive to performance and with the most portable software base. The VAX architecture was already facing stiff competition from mid-range systems based on standard high volume CISC microprocessors when RISC designs like MIPS, SPARC, and PA-RISC came along to administer the final blow. In the technical workstation market the Motorola 680X0 CISC family was easily overwhelmed by much faster RISC-based systems such as the ubiquitous SPARCstation-1.

The one market that RISC never got even a toehold in was the IBM-compatible PC market. Even the most popular RISC processors were manufactured in much smaller quantities than Intel x86 devices and could never effectively reach high volume PC price points without crippling their performance. Even if they could be built as cheaply as x86-based PCs, RISC processors couldn’t tap into the huge, non-portable software installed base except under emulation, which more than wiped out the RISC performance advantage. And much credit must go to Intel Corporation. It aggressively invested in both developing complex and innovative new ways of implementing the hopelessly CISC x86 ISA, and ensuring these would be implemented in each new generation of CMOS processes one or two years before any RISC processor. The potent combination was sufficient to ensure that x86 processors were never behind RISC processors in integer performance by a factor of two or more. This was a sufficient factor to ensure the continued loyalty of independent software vendors (ISVs) offering PC-based applications. An uneasy peace settled in between the two solitudes of x86 PCs and RISC high-end servers and workstations until late 1995 when the Intel Pentium Pro (P6) processor appeared.

The launch of the Pentium Pro processor was the computer industry equivalent of a Pearl Harbor type surprise attack directly against the RISC heartland: technical workstations and servers. The Pentium Pro combined an innovative new out-of-order execution superscalar x86 microprocessor with a separate high speed custom SRAM cache chip in a multi-chip module (MCM)-like package. The biggest surprise of all was the fact that the 0.35 um version debuted simultaneously with the expected 0.5 um version and more than six months ahead of Intel’s public product roadmap. This allowed the Pentium Pro to reach a clock speed of 200 MHz and integer performance levels that briefly eclipsed the fastest shipping RISC processor, the 0.5 um Alpha 21164.

The Pentium Pro’s integer performance lead didn’t last long and its floating point performance was still well behind nearly every RISC processor but this didn’t reduce the psychological impact. Any hope that RISC microprocessor vendors had of being able to reach PC price points with their much smaller volume chips, while offering a large enough integer performance advantage (x86 processors already provided sufficient floating point for nearly all PC-type applications) to entice the market away from x86 was pretty well extinguished.


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