Intel’s Plans for 3DXP DIMMs Emerge

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Intel will offer 3DXP-based DIMMs (previously codenamed Apache Pass) that use the DDR4 interface on the next-generation Cascade Lake server processor. The first DIMMs will be available in 128GB, 256GB, and 512GB capacities and work with a new software architecture for persistent memory. Intel and its partners have enabled the new persistent memory programming model for Java, Linux, VMware, and Windows and many customers are eagerly awaiting the non-volatile, high-capacity memory for in-memory databases and other applications.

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Intel’s 22FFL Process Improves Power, Cost, and Analog

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Intel’s 22FFL (FinFET Low-power) is a variant of their existing 22nm process that is aimed at low-cost, extremely low-power, and analog/RF applications. 22FFL relaxes the ground rules to reduce the need for double patterning, thereby cutting costs. At the same time, Intel’s engineers essentially backported the second and third generation FinFETs from the 10nm and 14nm processes to 22FFL, improving performance and power efficiency with superior fin geometry and workfunction metals. Intel also created a large library of digital and analog transistors and passive components.

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What’s Next for Moore’s Law? For Intel, III+V = 10nm QWFETs

On the eve of the 50th anniversary of Moore’s Law, the future of silicon CMOS is an open question. With rising costs and uncertain benefits, some semiconductor companies have questioned the wisdom of pursuing further scaling. I predict that Intel’s 10nm process technology will use Quantum Well FETs (QWFETs) with a 3D fin geometry, InGaAs for the NFET channel, and strained Germanium for the PFET channel, enabling lower voltage and more energy efficient transistors in 2016, and the rest of the industry will follow suit at the 7nm node.

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Adaptive Clocking in AMD’s Steamroller

My favorite paper from the ISSCC processor session describes an adaptive clocking technique implemented in AMD’s 28nm Steamroller core that compensates for power supply noise. Initial results show a 10-20% decrease in power consumption from reducing the voltage, with no loss in performance. This elegant technique is likely to be adopted across AMD’s entire product line including GPUs, x86 CPUs, ARM-based CPUs, and other critical blocks in highly integrated SoCs.

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ISSCC 2012 Preview

Highlights of the upcoming 2012 ISSCC include the first 22nm disclosures from Intel and several SoC papers from AMD, Cavium Networks and Oracle. Looking out further to the future, the clear focus is power consumption. There are several papers from Intel on low-power logic, one from IBM discussing 3D integration of embedded DRAM and a third from Fujitsu on system level power for the K supercomputer.

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Intel’s 22nm Tri-Gate Transistors

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For over 40 years, the planar transistor has been the keystone of the semiconductor industry. Intel’s new 22nm tri-gate transistor is revolutionary, moving transistors into a three dimensional world. After 10 years of research, this novel structure is the next step for Moore’s Law and promises to substantially improve performance and power efficiency.

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22nm Design Challenges at ISSCC 2011

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As Moore’s Law continues, each new generation of semiconductor manufacturing is ushered in by new challenges, hurdles and solutions. At ISSCC 2011, a panel with speakers from Global Foundries, IBM, Intel, Renesas and TSMC discussed manufacturing and circuit design interactions at the upcoming 22nm node. Industry leaders have reached a broad technical consensus, although with several subtle differences. This report explores the key challenges and solutions at 22nm; focusing on variation and co-optimization between design and manufacturing. As a result of the needed collaboration, understanding of physical design and manufacturing is even more critical to cutting edge chip development and achieving good performance, power and yields.

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IEDM 2010 Process Technology Update

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The integration predicted by Moore’s Law is fundamentally driven by advances in semiconductor manufacturing. One of the key challenges is scaling to ever finer and denser geometries, while improving the performance of transistors. IEDM and the VLSI Symposium are the premier venues to discuss the challenges and opportunities for future process technologies. No commercial 22nm process technologies were presented at IEDM 2010, but in the last two years a number of advances have been disclosed, both for high performance and low power applications. This article describes several 32nm and 28nm nodes from Intel, IBM’s Common Platform and TSMC, plus novel applications such as IBM’s 32nm eDRAM that have been disclosed at IEDM and VLSI.

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Exploring the Intel and Achronix Deal

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Intel recently announced they would manufacture 22nm FPGA’s for Achronix, a small start up. Intel’s process technology and fabs are the heart of the company. Opening up to third parties is a tremendous departure from the status quo – one that surprised and perplexed many people. Our analysis explores three possible explanations and infers that Intel is enabling complementary technologies rather than entering the foundry business.

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Process Technology at IEDM 2008

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David Kanter discusses 32nm process technologies presented at IEDM 2008 and VLSI 2009, including a discussion of high-k dielectrics and metal gates, immersion lithography and double patterning. Results from key manufacturers such as Intel, IBM/AMD, TSMC, Toshiba and others are discussed, analyzed and compared against previous generations using metrics for density (logic and SRAM) and switching speed metrics (for NFETs and PFETs).

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