David Kanter discusses 32nm process technologies presented at IEDM 2008 and VLSI 2009, including a discussion of high-k dielectrics and metal gates, immersion lithography and double patterning. Results from key manufacturers such as Intel, IBM/AMD, TSMC, Toshiba and others are discussed, analyzed and compared against previous generations using metrics for density (logic and SRAM) and switching speed metrics (for NFETs and PFETs).
The continuing pace of chip level feature miniaturization – Moore’s Law – has resulted in the doubling of the number of transistors per unit area approximately every couple of years. Chip designers have been provided with a plethora of transistor options to choose from in order to optimize for a given constraint. New materials with higher dielectric constants such as hafnium-based high-k gate oxide materials, along with metal gate electrodes, decrease leakage and boost drive current. Strained silicon engineering enables higher transistor switching speeds. Different transistor designs featuring multiple threshold voltages optimize for low power or high performance applications.
Manufacturing Versus Design With the announcement of the Core microarchitecture at Spring IDF of last year, Intel publicly stated their intentions to regain the lead in the world of x86 microprocessors. In a rather impressive fashion, the folks at Intel got down to business and executed almost flawlessly on their plans in 2006. Pretty much […]
A Historical Look at the VAX: DEC, NVAX, Alpha and the Competition [Part II] Editor’s Note and Introduction: This series of articles first appeared last summer in the comp.arch newsgroup, in a series of posts by John Mashey. Since then, it has been updated, edited and enriched with additional material and graphs by David Kanter, […]
Editor’s Note: This series of articles first appeared last summer in the comp.arch newsgroup, in a series of posts by John Mashey. Since then, it has been updated, edited and enriched with additional material and graphs by David Kanter, all with permission of the author. Introduction The VAX was an orthogonal, 32-bit CISC instruction set […]
Introduction The 2005 International Electron Devices Meeting (IEDM) was held in the Hilton Hotel on Connecticut Ave in Washington DC from December 4 through December 7. In the four day period, 1800 attendees from all over the world listened to and examined materials presented on the state of the art in the field of semiconductor […]
This article discusses three problems facing modern high performance MPU architects: decreasing returns from ILP, increasing power dissipation and relatively constant interconnect performance.
Partial coverage of IEDM 2003 Day 2, focusing on AMD and Intel process technologies