Peril of Proliferating Power
It is almost paradoxical that while the energy consumed by a single CMOS logic gate switching state has fallen exponentially with shrinking process feature size, the overall power consumption of MPUs has been steadily trending upwards at roughly 22% growth per year. This trend, shown in Figure 1 over the last 23 years, is due to the fact that the combined effect of growth in CPU complexity and operating frequency has exceeded the rate at which the energy used by individual logic elements to change state has fallen.
Figure 1 – Microprocessor Power Consumption, 1981 to Present
This trend has taken an ugly turn for the worse with the power dissipated by leakage current rapidly growing as process feature size falls from 180nm to 130nm and below. For example, leakage represents 5% of overall power of the 180 nm McKinley, or about 5 Watts. In the 130 nm Madison leakage grew to about 21% of power or about 22 Watts . Thus in a single process generation leakage power per unit area and per transistor went up by about 5x and 2.4x respectively.
In the distant past MPU power increased with growing design complexity and operating frequency but was offset by power supply voltage reductions that more or less tracked shrinking feature size. In the recent past, MPU power continued to increase with growing design complexity and operating frequency, but supply voltage scaling slowed to avoid performance scaling problems related to transistor threshold voltages. Since power dissipation can no longer be regulated by supply voltage scaling, MPU architects have turned to dynamic power management techniques. By adding tiny bits of extra logic that turn off unnecessary gate switching activity in unused portions of the MPU, designers have been able to constrain power consumption .
Today, architects are faced not only with the familiar upward pressures on power from growth in CPU complexity and operating frequency but also a rapid growth in leakage current power. At the same time power supply voltage scaling is continuing to slow while most of the low hanging fruit in the realm of dynamic power management has already been picked. The final and fatal blow to business as usual is that the practical engineering and economic limits of MPU cooling capabilities at the system level have already being reached in both high end servers and desktop PCs. That means that MPU architects are facing a situation where power considerations, rather than critical path timing, can limit maximum clock rate, and power budgeting becomes a zero-sum game of trade-offs between CPU complexity and CPU operating frequency. This latter consideration alone spells an end to the past practice of chasing diminishing ILP returns with wanton abandon. One might argue that if the thermal management issue was the only factor standing in the way, perhaps Seymour Cray-style heroic cooling efforts could allow the BBW bandwagon to rumble on for the design of MPUs for large and expensive servers and supercomputers. Unfortunately the third and final barrier facing BBW is as fundamental and immutable as the speed of light. This should hardly be surprising considering both limitations flow from the same set of equations.
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