The Incredible Shrinking CPU

Pages: 1 2 3 4 5 6 7 8 9

References

[1] Jourdan, S. et al, “Exploring Configurations of Functional Units in an Out-of-Order Superscalar Processor”, ISCA 1995 Digest of Technical Papers.

[2] Stinson, J. and Rusu, S., “A 1.5 GHz Third Generation Itanium Processor”, ISSCC 2003 Digest of Technical Papers.

[3] Montanaro, J. et al, “A 160 MHz, 32b 0.5 W CMOS RISC Microprocessor”, IEEE Journal of Solid-State Circuits, Vol. 31, No. 11, November 1996.

[4] Gochman, S. et al, “The Intel Pentium M Processor: Microarchitecture and Performance”, Intel Technology Journal, Vol. 7, Issue 2, May 21, 2003.

[5] Stinson, J. and Rusu, S., “A 1.5 GHz Third Generation Itanium 2 Processor”, DAC 2003 Digest of Technical Papers.

[6] Naffziger, S. and Hammond, G., “The Implementation of the Next Generation 64b Itanium Processor”, ISSCC 2002 Digest of Technical Papers.

[7] Anderson, C. et al, “Physical Design of a Fourth Generation POWER GHz Microprocessor”, ISSCC 2001 Digest of Technical Papers.

[8] Taur, Y., “CMOS Scaling and Issues in Sub-0.25 um Systems”, Design of High-Performance Microprocessor Circuits, IEEE Press, 2001, ISBN 0-7803-6001-X, p. 42.

[9] Reilly, M., “Clocks, Wires, and Physical Reality meets Schemes, Dreams, and Architecture”, ISSCC 2002, Microprocessor Design Workshop Technical Digest.

[10] Gelsinger, P., “Microprocessors for the New Millenium – Challenges, Opportunities and New Frontiers”, ISSCC 2001 Digest of Technical Papers.

[11] De, V. et al, ” Techniques for Leakage Power Reduction”, Design of High-Performance Microprocessor Circuits, IEEE Press, 2001, ISBN 0-7803-6001-X, p. 48.

[12] Barroso, L. et al, “Pirhana: A Scalable Architecture Based on Single-Chip Multiprocessing”, ISCA 2000, Technical Proceedings.


Pages: « Prev  1 2 3 4 5 6 7 8 9  

Discuss (11 comments)