Silvermont, Intel’s Low Power Architecture

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System Architecture

Collectively a pair of Silvermont cores and the shared L2 cache are described by Intel as a single module and form the building block for SoCs. Products will use 1-8 cores, depending on the market; smartphones are expected to favor dual-core solutions, with quad-cores for tablets and 8-cores for microservers. The L2 cache acts as the interface to the SoC fabric, which has been completely overhauled. Medfield and previous platforms use the old FSB infrastructure for coherent on-die communication. The new SoC fabric is based on the In-die Interface (IDI), which was used in Nehalem and Westmere.

IDI is a uni-directional, point-to-point link that connects each IP block (e.g., CPU cores + L2, graphics, system agent) to a global crossbar. The read and write channels are independently sized and governed by a credit-based flow control mechanism that delivers low latency for high utilization scenarios. Unlike the earlier FSB-based designs, transactions between IP blocks can occur out-of-order, reducing latency and improving system level performance. The system agent contains the memory controllers, which have much more extensive support for out-of-order memory transactions, compared to Saltwell.

A module shares a single voltage rail, but each core and the L2 cache is on a separate power gate. In theory, cores can operate at different frequencies, with the L2 cache at the higher frequency (likely using DLLs to adjust the frequency, as there is only a single PLL per module). From a practical standpoint asynchronous frequencies are unlikely to be desirable, since it adds latency for communication between different frequency domains and makes validation more difficult.

The older Saltwell core had higher latency software power management that was based on thermal headroom alone. Silvermont moves to much more flexible hardware power management, where the burst frequency is dynamically determined by thermal, electrical, and power delivery limits. This should translate into smaller guardbanding and significantly higher operating frequencies across the board.

The SoC fabric also includes mechanisms for global power management. Each IP block, whether designed by Intel or supplied by a third party such as Imagination Technologies, share a single power and thermal budget. This enables more advances power management techniques, such as shifting power from the CPU cores to the graphics when playing a game.

Silvermont Analysis

Intel claims that the core and system level microarchitectural improvements will yield 50% higher IPC for Silvermont versus the previous generation. Comparing the two microarchitectures in Figure 7, that is a highly plausible claim as out-of-order scheduling alone should be worth 30% and perhaps 5-10% for better branch prediction. Additionally, the 22nm process technology has reduced Vmin by around 100mV, and increased clock frequencies by roughly 20-30%. In total, this paints a very attractive picture for Silvermont.

Silvermont and Saltwell comparison

Figure 7. Silvermont and Saltwell Comparison (click to enlarge).

To cement this view, Intel compared Silvermont to Saltwell for tablets, showing performance data suggesting a 2× increase in CPU performance at constant power or a 5× reduction in power. Intel also claims a >60% performance and >3× power edge over projections for competing 28nm tablet SoCs expected later this year. In the more abstract realm of CPU to CPU comparisons, Intel indicated that Silvermont is a much faster design than the Cortex A7 or the A15 at any given power level; the goal is to avoid any complicated and high latency software-driven power management and rely on firmware-based management and power gating. As a design point, this is a good choice and follows in the steps of Apple’s Swift or Qualcomm’s Krait, which are undeniably successful CPU cores.

The usual caveats apply to any vendor supplied performance projections, as benchmarks are rather sensitive to software tuning and rely on numerous various assumptions about the future and system configurations. At this point, it would be far wiser to take any such numbers with a large grain of salt until real hardware is available and benchmarked. Missing performance or power projections by 10-20% is not uncommon, particularly for a new microarchitecture that may be challenging to model. But the gains claimed for Silvermont over Saltwell are too large to be lost to error bars.

Even if Intel’s projections are modestly optimistic, Silvermont should conclusively dispel the myth that the x86 instruction set is a barrier to power efficient microarchitecture. If Intel’s claims hold true, the Silvermont microarchitecture might be even more efficient than some ARM cores when normalized for Intel’s advantage in process technology. That seems an unlikely and counter-intuitive outcome, but could be explained by Intel’s larger teams and superb physical design.

Products based on Silvermont will launch in the latter half of 2013. Ironically, Merrifield will probably be the first 64-bit smartphone SoC, a milestone for a company that has traditionally lagged in this area. Merrifield should be very competitive for Android phones; if Intel also delivers a discrete LTE modem, it will inject competition into a market where Qualcomm has been unchallenged for quite some time. That being said, this is merely the starting point of a long battle for design wins in phones, especially given that the software ecosystem is ARM-centric. Silvermont is necessary for success, but hardly a guarantee.

Intel’s progress in tablets will accelerate with updated CPU cores, graphics, and SoC fabric. Windows tablets will be a particularly strong point, since Valleyview uses a variant of the Ivy Bridge GPU which is far better from a DirectX and OpenGL standpoint than pretty much every alternative. The Avoton server chip is already sampling to OEMs and should also be quite interesting. However, the impact will depend on whether networking, storage and other platform elements are integrated, which is crucial for microservers aimed at cloud computing.

In conclusion, the 22nm Silvermont CPU is a tremendous step forward, particularly in mobile devices. It is a thoroughly modern microarchitecture that is both higher performance and more efficient than the previous Saltwell core. The new core and updated SoC fabric and should put Intel on an even technical footing with mobile competitors such as Qualcomm, Nvidia, and Samsung, and perhaps even grant a significant advantage. Before the year is out, real performance and power measurements that demonstrate the impact of Silvermont will be available.

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