Bottleneck
The 400MHz, 6.4GB/s Itanium 2 system interface was fully adequate for the original McKinley and only a moderate constraint for Madison generation MPUs. But it is clear that maintaining backward compatibility would impose a major bottleneck on the 2+ GHz dual core multithreaded Montecito that would prevent the device from reaching its full performance potential on many types of applications despite the ample on-chip caches. But even a Montecito hobbled by backward compatibility still represents a substantial upgrade path for existing Itanium 2 systems and chipsets.
To solve this dilemma Intel will offer at least two versions of the Montecito. The legacy version will implement a 400MHz system interface and be packaged in the existing PAC611 module. It will serve as a drop-in replacement for the Madison 6M and the upcoming Madison 9M. The full capability, high performance version of Montecito will reportedly implement a 667MHz system interface. That transfer rate represents a 67% increase in system bandwidth, yet Intel has indicated that Montecito will offer over three times higher bandwidth than Madison [6]. That suggests that in addition to operating at the higher transfer rate the data path width will either be doubled to 256 bits or that two separate 128 bit wide data paths will be provided. The legacy package and full capability Montecito system interfaces are shown in Figure 5.
Figure 5 – Montecito Configurations
Although the 21GB/s system interface of the full capability Montecito will go a long way to close the massive per device bandwidth gap that POWER5 has opened over Madison, the new IPF chip clearly leaves system building – memory control, routing and scalability architecture entirely in the hands of others. Incredibly, the cancellation of its “Bayshore” chipset means that Intel can’t offer OEMs a standardized means to use the full capability Montecito. The two year old 870 chipset, which is used by Dell and value added resellers (VARs) of Intel white box systems, only supports the 6.4 GB/s legacy interface. Whether a deliberate tactic or a strategic mistake, Intel’s decision to cancel Bayshore means that the full performance capability of Montecito will be available only in the systems of OEMs which aggressively develop their own proprietary IPF chipsets.
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