How You Slice It
There is a clear difference in design strategy between Intel’s EPIC and IBM’s RISC high-end server processors. Intel chips are system agnostic – they embed capabilities but no choices and few assumptions about system level architecture in silicon. The interface between the MPU and system is a clean line of demarcation designed with as few signal crossings as possible to avoid the need for exotic and expensive packaging technology. Large multi-level integrated caches are provided to minimize data traffic across the interface and more efficiently allow 2 or 4 MPUs to share a bus segment (a capability sometimes mistaken as a requirement). In contrast, IBM chips can be considered as the silicon realization of a large-scale system architecture partitioned down to the granularity of two CPU cores. Because IBM sells both the MPU and the system it goes into, it has more freedom to partition in ways that greatly increases MPU signal count and the sophistication of packaging technology required at both the silicon and system level. This difference is shown in Figure 6.
Figure 6 – Intel and IBM System Partitioning
These two choices are basically driven by the clear difference in the business models of Intel and IBM. IBM is the greatest, and the last, of the vertically integrated computer OEMs. It designs and manufactures high-end server processors with the sole intention of selling them to customers safely wrapped within an IBM designed and manufactured system. As such, it doesn’t need to worry about creating silicon usable by other OEMs with inferior technical capabilities. In contrast, Intel is a component vendor whose end customers are most of the world’s computer OEMs, big and small, including IBM. Intel must design its MPUs to appeal to this large and diverse assortment of system designers and integrators, which differ tremendously in their wealth, engineering resources, and the markets they intend to address. Intel’s challenge is to create the highest possible performance MPU family that is still usable by a full cross section of OEMs with widely divergent system engineering capabilities; this necessitates conventional, relatively low pin count packaging. To maximize IPF performance, Intel exploits its inherent semiconductor design and manufacturing strength through the use of large die size devices combining compact full custom processor cores with massive fast caches.
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