Rambus Sets the Bandwidth Bar at a Terabyte/Second

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Data Tweaks and a Command and Addressing Overhaul

In general, the Terabyte Bandwidth Initiative is best viewed as the logical successor to the XDR2 memory interface, since in many regards it builds on that foundation but goes further towards being a narrow, high speed signaling interface.

32X Data Rate

The memory interface operates at 16gpbs; 32X the 500MHz reference clock. This requires an extremely accurate PLL that was designed specifically for this purpose. The 500MHz reference clock was chosen to reuse the infrastructure for the XDR, XDR2 and FlexIO interfaces, all of which use 500MHz input clocks.

The 32X data rate is a very evolutionary and predictable change to the data interface. With each generation, Rambus has consistently increased the ratio between the data interface and the reference clock. The original Direct Rambus interface operated at twice the reference clock and later evolved to four times the reference clock. The first generation of XDR transfered data at 8X the reference clock, and XDR2 increased the ratio to 16X. Hence it should come as no surprise that this new interface runs at 32X the reference clock.

FlexLink and Differential Signaling

To reduce area and increase performance, Rambus totally redesigned the command and addressing (C/A) link. Traditionally, commands and address information are sent over a parallel, multi-drop bus, with a drop for each DRAM – this is how XDR, DDR and GDDR all function. For instance, the XDR in the CELL processor used a 12 bit wide C/A interface that operated at 800Mbps, a quarter of the data rate. However, as data rates increase it becomes more and more difficult to synchronize multi-drop buses. To avoid this problem, Rambus moved from the old model of a 12 pin shared, parallel bus using slower single-end signaling to using the same techniques for both the data and address links. The new address link uses a 2 pin, point-to-point C/A link with differential signaling that operates at the full 16gbps data rate and builds on all of Rambus’ previous techniques for high performance (such as FlexPhase, a technique to compensate for skew). Rambus refers to the narrow, full speed C/A link as FlexLink, and the differential signaling for the C/A link as a Fully Differential Memory Architecture (Fully Differential since all three components, clocks data and C/A will be differential).

The two technologies are extremely complementary. Differential signaling avoids the capacitance and inductance problems with single-ended signals, so that the C/A link can operate at 16gbps and achieve the desired power profile at the transmitter. In turn, this frequency headroom enables fewer pins for the link. In general, high performance implementations of alternative technologies (XDR or GDDR) tend to use one C/A bus (12 or ~20 pins) for 1-2 DRAMs. Rambus’ new interface has 4-16 fewer C/A pins per DRAM than XDR and 16-32 fewer C/A pins than GDDR.

Both of these changes are very consistent with the overall trends for interconnect architectures in the semiconductor industry. Almost universally, interconnects have shifted away from the slow and wide buses that were favored in earlier days, such as SCSI or the front side bus. Instead physics and economics tend to favor interfaces with the fewest number of pins, where more bandwidth comes from faster signaling, rather than additional data pins. Rambus is somewhat ahead of the curve, as their memory interface is the first to use all differential signaling, and narrow point-to-point links. Since Rambus focuses primarily on the high bandwidth market, it is very likely that these architectural changes will be mirrored by more mainstream standards over the course of the next 2-4 years.

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