Rambus Sets the Bandwidth Bar at a Terabyte/Second

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Rambus’ Test Vehicle

Along with declaring their intentions to provide 1TB/s of bandwidth to ASICs, GPUs or MPUs in the future, Rambus also demonstrated a test vehicle for their future interconnect, shown below in Figure 2. The data eyes at the memory controller (with equalization) and the data eye at the DRAM (without equalization) are both at 16gbps.

Figure 2 – Rambus TB/s Test Vehicle

Rambus’ test system is manufactured in TSMC’s 65nm ASIC process and two DRAM emulators were manufactured using their 65nm DRAM process. The ASIC is flip chip packaged, while the DRAM emulators use wire bond – which is consistent with overall industry practices. The demo system does not use transmit equalization, which most high speed memory interfaces would employ in a real world situation.

At this point, Rambus declined to discuss the power efficiency (as measured in GB/s per mW) of this first implementation, or specific targets for the initiative. However, they did state that they do not believe the thermal envelop for memory interconnects has changed significantly since the time when XDR or XDR2 debuted. This implies that the power efficiency should increase by roughly the same factor as the bandwidth of an individual link relative to XDR2 or XDR. One of the advantages of setting a performance target twice as high as the estimated needs of the target systems is that a system designer can easily trade that extra performance for even lower power consumption.

Rambus did not quantitatively describe the project targets or implementation specific bit-error rates (BER), other than to say that they will provide “commercially viable BERs”. The achievable level of BERs is to a large extent implementation specific (depending on board quality, etc.), and is not defined wholly by Rambus’ IP. One challenge that they are cognizant of is that maintaining acceptable failure rates requires lower and lower BERs as bandwidth increases. While a given error rate may be acceptable at 4gbps and yield a 3-5 year expected life time, at 16gbps that same error rate will produce an expected life time that is one fourth as long – below most commercial requirements. Consequently, Rambus will design for lower BERs and help any customers achieve the desired level of reliability.


As Rambus was very clear to point out, this announcement isn’t about a currently shipping product – it is about setting goals. These goals are certainly aggressive, but Rambus has made substantial progress already and there is little risk that they would fall short of their targets. Rambus’ work in this area is extremely relevant for the console and graphics markets. When this technology is finally productized, the initial design wins are most likely to be in next generation consoles, particularly designs from Sony, given their previous experience. The most interesting aspect of the technology that Rambus has discussed are the implications for other interconnects. It will be very interesting to see when other interconnects follow suit and transition command and address communication towards narrow high speed differential links instead of slower and wider single ended buses.

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