ISSCC 2006: Intel Tulsa

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The third paper in the microprocessor track concerned Tulsa, a badly needed 65nm Xeon MP processor. From a product stand point, Intel is currently weakest in 4-socket systems. The front side bus is a perfectly fine solution at 2 sockets, but scalability tapers off at 4 sockets, while point to point interconnects work more efficiently. Tulsa is likely to be the last Pentium 4 based MPU launched, and was specifically designed to address issues in Intel’s system architecture.

Figure 1 – Tulsa Die Micrograph, courtesy of Intel

Tulsa is based on Cedar Mill, with 1MB L2 cache per core, augmented by 16MB of inclusive shared L3 cache, which is accessed through a unified (and presumably FIFO) queue. This server MPU uses 1.3B transistors (121M/core) and 435mm2 in Intel’s high performance bulk 65nm process (see David Wang’s IEDM coverage) with 8 layers of copper interconnect. Tulsa will run at 3.4GHz with 1.25V, and a 150W TDP and 110W average power. Intel’s *Ts are also supported: virtualization, demand based switching and dynamic cache line disabling (upto 32 lines). With a BIOS upgrade, Tulsa is drop in compatible with the Twin Castle chipset. Figure 1 above shows a die photo of Tulsa.

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