Intel Goes Long for a Power Play
Intel has also slightly changed their low power techniques for Tulsa. Rather than using multiple threshold transistors (for example, the high and low Vt in Prescott or triple Vt as in AMD’s process), Intel has chosen to use transistors with varying L effective (Le). Le is the distance between the source and drain as depicted below in Figure 2.
Figure 2 – Le and Sub-threshold Leakage, courtesy of Paul DeMone
The red arrow illustrates sub-threshold leakage, where current leaks from the drain to the source. Sub-threshold leakage is currently the dominant form of leakage in advanced processes. The longer Le is, the harder it is for current to seep from the drain to the source. Intel reports that using transistors with 10% longer Le reduces leakage by 3x. Intel designers used long Le transistors on all paths with timing slack; about 52% of core transistors (which constitute 56% of total transistor length) and all of the L3 data arrays are long Le. Figure 3 below shows the density of long Le transistors in Tulsa.
Figure 3 – Long Le transistor usage in Tulsa, courtesy of Intel
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