A Historical Look at the VAX: DEC, NVAX, Alpha and Competitors

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A Historical Look at the VAX: DEC, NVAX, Alpha and the Competition [Part II]

Editor’s Note and Introduction:

This series of articles first appeared last summer in the comp.arch newsgroup, in a series of posts by John Mashey. Since then, it has been updated, edited and enriched with additional material and graphs by David Kanter, all with permission of the author. John Mashey is a well respected operating system developer and computer architect; he has worked at Bell Labs, Convergent, MIPS and retired from SGI as VP and Chief Scientist.

The first article in this series largely dealt with the economics of microprocessors and computer systems. In particular, the trade-offs between a fabbed and fabless model were discussed, and the incredible benefits of volume for a semiconductor company. This second article looks at the competitive position of the VAX during the rise of RISC architectures, in the late 1980’s and early 1990’s.

DEC (at least some people) understood the importance of VLSI CMOS and that good silicon design can have excellent results. DEC had excellent CPU and systems designers, software people, and invested in fabs (for better or worse – some of us could never quite figure out how they could afford the fabs in the 1990s). They had some superb circuit designers, who even impressed some of the best circuit designers I’ve known.

However, in the 1980s, they never had more than about 100 VLSI CPU designers, which in practice meant that at any one time, they could realistically be doing one brand new design, and one shrink or variation. Of course, they were also doing the ECL VAX9000 mainframe, but that was a whole different organization.

The problem that DEC faced was that their VAX cash cow was under attack, and they simply couldn’t figure out how to keep the VAX competitive. This was first seen in the technical markets, where PA-RISC, SPARC, and MIPS started out. Eventually, PA-RISC migrated to the commercial market and began to pose a threat there as well. I think Robert Supnik’s foreward in the Digital Technical Journal described this reasonably well.

As a good head-to-head comparison, NVAX and the Alpha 20164 were built:

  • in same process
  • about the same time
  • with the same design tools
  • with similar-sized teams

Moreover, the NVAX team had already implemented pipelined CMOS VAXen before, and had a long history of diagnostics, test programs, behavioral statistics, etc. while the Alpha team had far fewer resources and experience to call upon. So the extent that there was an advantage, it was certainly in favor of the NVAX team.

As a result of the ISA differences between VAX and Alpha, the NVAX team had to spend a lot more effort on micro-architecture, whereas the Alpha team could spend that effort on aggressive implementation. The NVAX/NVAX+ was only able to hit 80-90MHz, while the 21064 was running at 200MHz and was superscalar to boot. The end result was that the 21064 vastly outperformed the NVAX/NVAX+.

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