A Historical Look at the VAX: DEC, NVAX, Alpha and Competitors

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The Competition’s Performance Vexes DEC

The prior example of the NVAX/NVAX+ and the Alpha 21064 serves to illustrate the implementation advantages of a clean RISC architecture. Despite similar resources, which if anything favored the NVAX/NVAX+, the Alpha 21064 performed roughly 3x better in SPECint89 and 5x better on SPECfp89. RISC designs were much simpler which lead to substantial performance benefits, consequently this created a difficult competitive environment for the VAX. The table below includes quite a few systems from the early 1990’s, most of which were released around 1992 (give or take a year) and several systems from mid 1990’s as well.

Table 1 – Performance and Characteristics of VAX and Competing Systems

I started with SPEC89 numbers for VAXen, because I cannot find SPEC92 numbers. Then I made a gross estimate of the equivalent SPEC92 scores, so that all of the machines are on the same scale, noting of course that benchmarks degrade over time due to compiler-cracking. The asterisked SPECfp89 scores include the effect of the heightened matrix300 numbers (NB: matrix300 was a subtest that certain compilers were able to ‘crack’, producing what some felt were unrealistic performance gains, this also happened to 179.art in SPECcpu2000). I used the highest NVAX numbers I had handy, from my old paper SPEC Newsletters. I am ignoring costs, and the dates in the table must be taken with lots of salt, for numerous reasons, and as always SPECint and SPECfp are not everything (spoken as an old OS person).

The NVAX shipped in 4Q91, and the NVAX+ in 1992. The first R4000s shipped in systems in 1Q92, so these are contemporaneous, as they are with 486DX and 486DX2.

The NVAX+ performs at about 75-80% of a MIPS R4000 on integer and FP here, despite using a better process (0.75um, 3-metal versus 1.0um, 2-metal), a larger die (237mm2 versus 184mm2), and being 32-bit rather than 64-bit. As a side note, it is somewhat an accident of history and business arrangements that the R4000 was done in 2-metal. The original plan called for a 2-issue superscalar MPU, but the 2-metal process forced the designers to opt for a super pipelined, 1-issue instead. As a result, the R4000/R4400 often had lower SPECfp numbers than the contemporaneous HP and IBM RISCs. To compensate, it sometimes had better integer performance, and sometimes could afford bigger L2 caches, because the R4000/R4400s were relatively small.

In any case, with respect to SPEC FP performance, in late 1992, the fastest NVAX+ was outperformed by IBM, HP, MIPS, Sun (maybe), and Alpha (by 3-4X). The NVAX+ was 3X faster than a 66MHz 486DX2. In SPECint, in late 1992, the NVAX was outperformed, generally by the RISCs…but worse, there wasn’t much daylight between it and a 66MHZ 486DX2, or even a 50MHz 486DX.

The real problem of course (not just for the VAX, but for everyone), was the last entry in Table 1. Intel had the resources and volume to “pipeline” major design teams (Santa Clara and Portland) plus variants and shrinks, and there was an incredible proliferation in these years. Hence it is also instructive to compare the NVAX+ with Intel’s entries, which are found in the right part of the table.

Suppose you were a VAX customer in 1992. If you were using VAX/VMS for:

  • Commercial application, then you were committed to VMS for a long time.
  • Technical applications (FP intensive), then RISC competitors keep coming by with their rather attractive numbers
If you were using Ultrix (Digital’s UNIX for VAX) for:
  • FP applications, then the RISC competitors were looking pretty attractive
  • Integer applications, not only are the RISC competitors looking good, but Intel was getting close to parity on performance

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