A Historical Look at the VAX: DEC, NVAX, Alpha and Competitors

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Could DEC Have Done it?

I’m not going to comment on DEC’s handling of Alpha, fabs, announcements and alternate strategy variations. But this part should make clear that there was real pressure on the VAX architecture, from above (in terms of performance) and below (Intel coming up).

One might imagine, that had there been no Alpha, and had everybody at Hudson had kept working on VAXen, that they could have gotten a 2-issue superscalar (like the Pentium), in 1994. Alternatively, they could have made an out-of-order CPU (like Pentium Pro) in 1996 perhaps as well as doing the required shrinks and variants.

From the resources I’ve heard described, I find it very difficult to believe they could have done both a Pentium-class chip and a Pentium Pro-class chip simultaneously (and note, world-class design teams do not grow on trees). I could be convinced otherwise, but as one of the NVAX designers says, only by “members of the NVAX and Alpha design teams, plus Joel Emer”, i.e., well-informed people.

Moreover, technical feasibility is not enough by itself. The real challenges would have been sustaining a customer base in face of incredibly strong competitive pressure mentioned previously and getting these hypothetical superscalar and out-of-order VAXes to market in a timely fashion.

In Part III, I’ll sketch some of the tough issues for implementing the VAX, as best I can. In particular, I will note the ISA features that might make things harder for VAX than for x86, to do 2 or 4-issue superscalar, or a full blown out-of-order design. In particular, what this means is that you can implement a type of microarchitecture, but it gains you more or less performance dependent on the ISA and the rest of the microarchitecture. For instance, the NVAX design at one point was going to decode 2 specifiers per cycle, but it was found to add too much complexity and only get a 2% performance increase.

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