Chip Design and Economics
Most people probably know the old project management adage: “features, cost, schedule: you pick two, I’ll tell you the other.”
In CPU design, there are currently several alternatives, arranged in order from cheapest to most expensive to design they are:
- Structured ASIC
- ASIC, full synthesized logic
- Custom, with some synthesized and some custom logic or layout design and maybe with some special circuit design.
Better tools help, but they are expensive, especially because people pushing the cutting edge tend to need to build some of their own. An FPGA will be big, use more power, and run at lower clock rate than the alternatives. The more customized a chip is, the faster it can go, but it either takes more people, or longer to design, and usually both.
Larger companies, like Intel, sometimes have one design team produce an original device using a lot of synthesized logic, and then another team comes right behind them. The second team will use the same logic, but tunes the critical paths for higher clock rates, shrinks the die using more custom design, works to get higher yields, etc. Put another way, if you have enough volume, and good ASPs, you can afford to spend a lot of engineering effort to tune designs, enough to overcome ISA problems.
We would like to take this opportunity to thank several people who have been kind enough to provide us with input on this series of articles:
- Bob Colwell
- Andy Glew
- Andy Goldstein
- Dileep Bhandarkar
- Sue Skonetski
We appreciate your input and expertise in your respective areas.
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