The second major area of interest at the VLSI Symposium was novel memory technologies. Historically, most companies have sat on the sidelines with only modest efforts in emerging memories. The payoff for a new memory is potentially huge, but the required investment is correspondingly daunting. The three major memory types – SRAM, DRAM, and NAND – are so mature and well-optimized; most companies realize that sets a high hurdle. However, the debut of Intel and Micron’s 3DXP has woken the industry up and is acting as a catalyst for investment in other memory types.
MRAM is an emerging memory that is already in production. A full description of the technology is beyond the scope of this article. Briefly, the memory works by manipulating magnetic materials to modulate the resistance of a magnetic tunnel junction (or MTJ) cell. The MTJs are non-volatile, use CMOS-compatible voltages, and are formed in the metal layers without disturbing the critical transistor formation process flows. MRAM is denser than SRAM, but the memory cells are about 50% larger than comparable eDRAM. Moreover, MRAM appears to scale very nicely to smaller feature sizes whereas SRAM scaling has slowed in recent years; some companies hope that one day MRAM can replace SRAM for large arrays. MRAM is also much faster than flash, with latencies close to DRAM.
Everspin Technologies offers several generations of MRAM-based discrete memory products using standard DDR3 and DDR4 interfaces. Other companies are interested in MRAM as a memory that is embedded in a modern logic process technology. However, MRAM comes with its own share of challenges. Two interesting papers at the VLSI Symposium described some of these problems and proposed potential solutions.
TDK Focuses on New Materials
A first paper from TDK describes a new STT-MRAM cell design that the company claims is attractive for sub-10nm logic process technologies. The goal was to achieve a bit-cell that is compact, operates at low-voltage, and is sufficiently reliable with low write errors.
Generally, the switching voltage of a STT-MRAM bit-cell is determined by the product of the resistance and the area of the MTJ (described as the RA). Using new materials, the team created a small MTJ with a 30nm diameter and lower (but undisclosed) RA that can switch at less than 300mV. This should enable integration on a chip that operates at roughly 0.5V. The smaller MTJ also requires less energy (0.12pJ) to switch, and can be written using either a 10ns pulse that is 50μA or a 20ns pulse that is 35μA. For the shorter write pulse at 270mV, the team demonstrated that the write error rate was under 1-9.
TSMC Designs for Easier Reading
A second paper from TSMC addressed another problem, using an entirely different set of techniques. One of the drawbacks of MTJs is the small read window; the difference between high- and low-resistance states in an MTJ is typically 2-3X. By way of comparison, Intel’s 22FFL process features fast transistors that leak 10nA/μm and achieve drive currents of 1.22mA/μm – a difference of more than 100,000X. As a result, sensing the value of an MTJ bit-cell is much more difficult than an SRAM bit-cell.
Unfortunately, building an MRAM array compounds this problem further. To build a compact and efficient memory array, many small MTJ cells are formed in fine-pitch interconnect layers and connected on a shared bitline. The more cells on the bitline, the greater the variation between the near and far cells. Similarly, a good array will share other wiring (sourceline and wordline) between multiple cells to better amortize the area overhead. To achieve good density, the array should ideally use fine-pitch metal layers for the wiring, but the smaller wires are more susceptible to variation. Each of these cumulative sources of variation eats away at the already small read window.
The TSMC team turned to a more complicated sensing circuit design to overcome the small read window for a 16Mbit array implemented in a 40nm CMOS process. The array is organized into long bitlines that span 1,024 cells and wordlines that span 8 cells. The reference cells are put in series with a resistor that is tuned to precisely shift the reference cells into the center of the read window. TSMC employs current-mode latch sense amplifiers that are enhanced with calibration and trimming for each sense amplifier to mitigate process variations. In addition, the sense amplifiers use the trim values to compensate for the difference in current from the top half and bottom half of the long bitlines, increasing the read window by 20%. The calibration and trimming is performed during manufacturing.
Overall, the 16Mbit array consumed 3.03mm2 in TSMC’s 40nm logic process and the company reported a 17.5ns access time using a 1.1V Vdd over a -40C-125C temperature range.
Both the TDK and TSMC papers highlight challenges to MRAM adoption and offer potential solutions. The two teams take strikingly different approaches. TDK favors material science and manufacturing techniques to improve the underlying MTJs with a focus on scaling down the bitcell and improving the write behavior. The data is not for full arrays and some characteristics such as endurance cannot be extrapolated from a small sample of cells to an array or to high-volume manufacturing. The TSMC work aims to improve the read behavior of modest sized arrays with clever circuit design that mitigates the imperfections in the underlying media.
Neither paper describes a technology that is ready for high-volume manufacturing. But both teams highlight the low-hanging research opportunities that are available for an emerging memory such as MRAM. The two papers also illustrate the great commercial interest in developing MRAM. As Moore’s Law slows, semiconductor manufacturers must turn to new techniques to boost performance, and new memories, such as MRAM, could fill that void. Each emerging memory will require considerable research to pick the low-hanging fruit and find a commercially viable niche that will support high-volume manufacturing.
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