At VLSI 2018, researchers from TDK and TSMC described advances in Magneto-resistive memory (MRAM). TDK focused on new materials to improve writing for low-voltage MRAM cells at small geometries. A team from TSMC showcased circuit techniques to improve read performance of MRAM arrays despite process variability and a small read window.
IBM presented a neural network accelerator at VLSI 2018 showcasing a variety of architectural techniques for machine learning, including a regular 2D array of small processing elements optimized for dataflow computation, reduced precision arithmetic, and explicitly addressed memories.
Graphics is a focal point of the upcoming Haswell platform, necessitating a high bandwidth memory solution. To deliver high performance Intel is returning to the DRAM market, which it exited in 1985. The memory that ships with Haswell will be a custom embedded DRAM mounted in the package and manufactured on a variant of Intel’s 22nm process. By avoiding the commodity memory market, Intel will preserve high margins by cannibalizing discrete GPUs and dedicated graphics memory.
The integration predicted by Moore’s Law is fundamentally driven by advances in semiconductor manufacturing. One of the key challenges is scaling to ever finer and denser geometries, while improving the performance of transistors. IEDM and the VLSI Symposium are the premier venues to discuss the challenges and opportunities for future process technologies. No commercial 22nm process technologies were presented at IEDM 2010, but in the last two years a number of advances have been disclosed, both for high performance and low power applications. This article describes several 32nm and 28nm nodes from Intel, IBM’s Common Platform and TSMC, plus novel applications such as IBM’s 32nm eDRAM that have been disclosed at IEDM and VLSI.